alt_synch_pipe_mc8.tdf

altera fpga 和ts201的linkport接口设计

--dffpipe DELAY=3 WIDTH=7 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF
--VERSION_BEGIN 11.1 cbx_a_gray2bin 2011:10:31:21:11:05:SJ cbx_a_graycounter 2011:10:31:21:11:05:SJ cbx_altdpram 2011:10:31:21:11:05:SJ cbx_altsyncram 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_dcfifo 2011:10:31:21:11:05:SJ cbx_fifo_common 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_counter 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_lpm_mux 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_scfifo 2011:10:31:21:11:05:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ  VERSION_END


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FUNCTION dffpipe_gd9 (clock, clrn, d[6..0])
RETURNS ( q[6..0]);

--synthesis_resources = lut 21 
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF";

SUBDESIGN alt_synch_pipe_mc8
( 
	clock	:	input;
	clrn	:	input;
	d[6..0]	:	input;
	q[6..0]	:	output;
) 
VARIABLE 
	dffpipe9 : dffpipe_gd9;

BEGIN 
	dffpipe9.clock = clock;
	dffpipe9.clrn = clrn;
	dffpipe9.d[] = d[];
	q[] = dffpipe9.q[];
END;
--VALID FILE