lp_rx_top_stratix.hier_info

altera fpga 和ts201的linkport接口设计

|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rdbuw
clock => dffe8a[6].CLK
clock => dffe8a[5].CLK
clock => dffe8a[4].CLK
clock => dffe8a[3].CLK
clock => dffe8a[2].CLK
clock => dffe8a[1].CLK
clock => dffe8a[0].CLK
clrn => dffe8a[6].ACLR
clrn => dffe8a[5].ACLR
clrn => dffe8a[4].ACLR
clrn => dffe8a[3].ACLR
clrn => dffe8a[2].ACLR
clrn => dffe8a[1].ACLR
clrn => dffe8a[0].ACLR
d[0] => dffe8a[0].IN0
d[1] => dffe8a[1].IN0
d[2] => dffe8a[2].IN0
d[3] => dffe8a[3].IN0
d[4] => dffe8a[4].IN0
d[5] => dffe8a[5].IN0
d[6] => dffe8a[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rdusedw
clock => dffe8a[6].CLK
clock => dffe8a[5].CLK
clock => dffe8a[4].CLK
clock => dffe8a[3].CLK
clock => dffe8a[2].CLK
clock => dffe8a[1].CLK
clock => dffe8a[0].CLK
clrn => dffe8a[6].ACLR
clrn => dffe8a[5].ACLR
clrn => dffe8a[4].ACLR
clrn => dffe8a[3].ACLR
clrn => dffe8a[2].ACLR
clrn => dffe8a[1].ACLR
clrn => dffe8a[0].ACLR
d[0] => dffe8a[0].IN0
d[1] => dffe8a[1].IN0
d[2] => dffe8a[2].IN0
d[3] => dffe8a[3].IN0
d[4] => dffe8a[4].IN0
d[5] => dffe8a[5].IN0
d[6] => dffe8a[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rs_dbwp
clock => dffe8a[6].CLK
clock => dffe8a[5].CLK
clock => dffe8a[4].CLK
clock => dffe8a[3].CLK
clock => dffe8a[2].CLK
clock => dffe8a[1].CLK
clock => dffe8a[0].CLK
clrn => dffe8a[6].ACLR
clrn => dffe8a[5].ACLR
clrn => dffe8a[4].ACLR
clrn => dffe8a[3].ACLR
clrn => dffe8a[2].ACLR
clrn => dffe8a[1].ACLR
clrn => dffe8a[0].ACLR
d[0] => dffe8a[0].IN0
d[1] => dffe8a[1].IN0
d[2] => dffe8a[2].IN0
d[3] => dffe8a[3].IN0
d[4] => dffe8a[4].IN0
d[5] => dffe8a[5].IN0
d[6] => dffe8a[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp
clock => dffpipe_gd9:dffpipe9.clock
clrn => dffpipe_gd9:dffpipe9.clrn
d[0] => dffpipe_gd9:dffpipe9.d[0]
d[1] => dffpipe_gd9:dffpipe9.d[1]
d[2] => dffpipe_gd9:dffpipe9.d[2]
d[3] => dffpipe_gd9:dffpipe9.d[3]
d[4] => dffpipe_gd9:dffpipe9.d[4]
d[5] => dffpipe_gd9:dffpipe9.d[5]
d[6] => dffpipe_gd9:dffpipe9.d[6]


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp|dffpipe_gd9:dffpipe9
clock => dffe10a[6].CLK
clock => dffe10a[5].CLK
clock => dffe10a[4].CLK
clock => dffe10a[3].CLK
clock => dffe10a[2].CLK
clock => dffe10a[1].CLK
clock => dffe10a[0].CLK
clock => dffe11a[6].CLK
clock => dffe11a[5].CLK
clock => dffe11a[4].CLK
clock => dffe11a[3].CLK
clock => dffe11a[2].CLK
clock => dffe11a[1].CLK
clock => dffe11a[0].CLK
clock => dffe12a[6].CLK
clock => dffe12a[5].CLK
clock => dffe12a[4].CLK
clock => dffe12a[3].CLK
clock => dffe12a[2].CLK
clock => dffe12a[1].CLK
clock => dffe12a[0].CLK
clrn => dffe10a[6].ACLR
clrn => dffe10a[5].ACLR
clrn => dffe10a[4].ACLR
clrn => dffe10a[3].ACLR
clrn => dffe10a[2].ACLR
clrn => dffe10a[1].ACLR
clrn => dffe10a[0].ACLR
clrn => dffe11a[6].ACLR
clrn => dffe11a[5].ACLR
clrn => dffe11a[4].ACLR
clrn => dffe11a[3].ACLR
clrn => dffe11a[2].ACLR
clrn => dffe11a[1].ACLR
clrn => dffe11a[0].ACLR
clrn => dffe12a[6].ACLR
clrn => dffe12a[5].ACLR
clrn => dffe12a[4].ACLR
clrn => dffe12a[3].ACLR
clrn => dffe12a[2].ACLR
clrn => dffe12a[1].ACLR
clrn => dffe12a[0].ACLR
d[0] => dffe10a[0].IN0
d[1] => dffe10a[1].IN0
d[2] => dffe10a[2].IN0
d[3] => dffe10a[3].IN0
d[4] => dffe10a[4].IN0
d[5] => dffe10a[5].IN0
d[6] => dffe10a[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw
clock => dffe8a[6].CLK
clock => dffe8a[5].CLK
clock => dffe8a[4].CLK
clock => dffe8a[3].CLK
clock => dffe8a[2].CLK
clock => dffe8a[1].CLK
clock => dffe8a[0].CLK
clrn => dffe8a[6].ACLR
clrn => dffe8a[5].ACLR
clrn => dffe8a[4].ACLR
clrn => dffe8a[3].ACLR
clrn => dffe8a[2].ACLR
clrn => dffe8a[1].ACLR
clrn => dffe8a[0].ACLR
d[0] => dffe8a[0].IN0
d[1] => dffe8a[1].IN0
d[2] => dffe8a[2].IN0
d[3] => dffe8a[3].IN0
d[4] => dffe8a[4].IN0
d[5] => dffe8a[5].IN0
d[6] => dffe8a[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw
clock => dffe8a[6].CLK
clock => dffe8a[5].CLK
clock => dffe8a[4].CLK
clock => dffe8a[3].CLK
clock => dffe8a[2].CLK
clock => dffe8a[1].CLK
clock => dffe8a[0].CLK
clrn => dffe8a[6].ACLR
clrn => dffe8a[5].ACLR
clrn => dffe8a[4].ACLR
clrn => dffe8a[3].ACLR
clrn => dffe8a[2].ACLR
clrn => dffe8a[1].ACLR
clrn => dffe8a[0].ACLR
d[0] => dffe8a[0].IN0
d[1] => dffe8a[1].IN0
d[2] => dffe8a[2].IN0
d[3] => dffe8a[3].IN0
d[4] => dffe8a[4].IN0
d[5] => dffe8a[5].IN0
d[6] => dffe8a[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_ws_dgrp
clock => dffpipe_gd9:dffpipe9.clock
clrn => dffpipe_gd9:dffpipe9.clrn
d[0] => dffpipe_gd9:dffpipe9.d[0]
d[1] => dffpipe_gd9:dffpipe9.d[1]
d[2] => dffpipe_gd9:dffpipe9.d[2]
d[3] => dffpipe_gd9:dffpipe9.d[3]
d[4] => dffpipe_gd9:dffpipe9.d[4]
d[5] => dffpipe_gd9:dffpipe9.d[5]
d[6] => dffpipe_gd9:dffpipe9.d[6]


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_ws_dgrp|dffpipe_gd9:dffpipe9
clock => dffe10a[6].CLK
clock => dffe10a[5].CLK
clock => dffe10a[4].CLK
clock => dffe10a[3].CLK
clock => dffe10a[2].CLK
clock => dffe10a[1].CLK
clock => dffe10a[0].CLK
clock => dffe11a[6].CLK
clock => dffe11a[5].CLK
clock => dffe11a[4].CLK
clock => dffe11a[3].CLK
clock => dffe11a[2].CLK
clock => dffe11a[1].CLK
clock => dffe11a[0].CLK
clock => dffe12a[6].CLK
clock => dffe12a[5].CLK
clock => dffe12a[4].CLK
clock => dffe12a[3].CLK
clock => dffe12a[2].CLK
clock => dffe12a[1].CLK
clock => dffe12a[0].CLK
clrn => dffe10a[6].ACLR
clrn => dffe10a[5].ACLR
clrn => dffe10a[4].ACLR
clrn => dffe10a[3].ACLR
clrn => dffe10a[2].ACLR
clrn => dffe10a[1].ACLR
clrn => dffe10a[0].ACLR
clrn => dffe11a[6].ACLR
clrn => dffe11a[5].ACLR
clrn => dffe11a[4].ACLR
clrn => dffe11a[3].ACLR
clrn => dffe11a[2].ACLR
clrn => dffe11a[1].ACLR
clrn => dffe11a[0].ACLR
clrn => dffe12a[6].ACLR
clrn => dffe12a[5].ACLR
clrn => dffe12a[4].ACLR
clrn => dffe12a[3].ACLR
clrn => dffe12a[2].ACLR
clrn => dffe12a[1].ACLR
clrn => dffe12a[0].ACLR
d[0] => dffe10a[0].IN0
d[1] => dffe10a[1].IN0
d[2] => dffe10a[2].IN0
d[3] => dffe10a[3].IN0
d[4] => dffe10a[4].IN0
d[5] => dffe10a[5].IN0
d[6] => dffe10a[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_ws_nbrp
clock => dffe8a[6].CLK
clock => dffe8a[5].CLK
clock => dffe8a[4].CLK
clock => dffe8a[3].CLK
clock => dffe8a[2].CLK
clock => dffe8a[1].CLK
clock => dffe8a[0].CLK
clrn => dffe8a[6].ACLR
clrn => dffe8a[5].ACLR
clrn => dffe8a[4].ACLR
clrn => dffe8a[3].ACLR
clrn => dffe8a[2].ACLR
clrn => dffe8a[1].ACLR
clrn => dffe8a[0].ACLR
d[0] => dffe8a[0].IN0
d[1] => dffe8a[1].IN0
d[2] => dffe8a[2].IN0
d[3] => dffe8a[3].IN0
d[4] => dffe8a[4].IN0
d[5] => dffe8a[5].IN0
d[6] => dffe8a[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|add_sub_bvb:lpm_add_sub_rd_udwn
dataa[0] => _.IN0
dataa[0] => _.IN0
dataa[0] => _.IN0
dataa[1] => _.IN0
dataa[1] => _.IN0
dataa[1] => _.IN0
dataa[2] => _.IN0
dataa[2] => _.IN0
dataa[2] => _.IN0
dataa[3] => _.IN0
dataa[3] => _.IN0
dataa[3] => _.IN0
dataa[4] => _.IN0
dataa[4] => _.IN0
dataa[4] => _.IN0
dataa[5] => _.IN0
dataa[5] => _.IN0
dataa[5] => _.IN0
dataa[6] => _.IN0
dataa[6] => _.IN0
dataa[6] => _.IN0
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0
datab[4] => datab_node[4].IN0
datab[5] => datab_node[5].IN0
datab[6] => datab_node[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|add_sub_bvb:lpm_add_sub_wr_udwn
dataa[0] => _.IN0
dataa[0] => _.IN0
dataa[0] => _.IN0
dataa[1] => _.IN0
dataa[1] => _.IN0
dataa[1] => _.IN0
dataa[2] => _.IN0
dataa[2] => _.IN0
dataa[2] => _.IN0
dataa[3] => _.IN0
dataa[3] => _.IN0
dataa[3] => _.IN0
dataa[4] => _.IN0
dataa[4] => _.IN0
dataa[4] => _.IN0
dataa[5] => _.IN0
dataa[5] => _.IN0
dataa[5] => _.IN0
dataa[6] => _.IN0
dataa[6] => _.IN0
dataa[6] => _.IN0
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0
datab[4] => datab_node[4].IN0
datab[5] => datab_node[5].IN0
datab[6] => datab_node[6].IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|cntr_cua:rdptr_b
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|cntr_cua:wrptr_b
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
aclr => counter_cella5.ACLR
aclr => counter_cella6.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cnt_en => counter_cella5.DATAB
cnt_en => counter_cella6.DATAB