lp_rx_top_stratix.hier_info

altera fpga 和ts201的linkport接口设计

address_b[1] => ram_block7a10.PORTBADDR1
address_b[1] => ram_block7a11.PORTBADDR1
address_b[1] => ram_block7a12.PORTBADDR1
address_b[1] => ram_block7a13.PORTBADDR1
address_b[1] => ram_block7a14.PORTBADDR1
address_b[1] => ram_block7a15.PORTBADDR1
address_b[1] => ram_block7a16.PORTBADDR1
address_b[1] => ram_block7a17.PORTBADDR1
address_b[1] => ram_block7a18.PORTBADDR1
address_b[1] => ram_block7a19.PORTBADDR1
address_b[1] => ram_block7a20.PORTBADDR1
address_b[1] => ram_block7a21.PORTBADDR1
address_b[1] => ram_block7a22.PORTBADDR1
address_b[1] => ram_block7a23.PORTBADDR1
address_b[1] => ram_block7a24.PORTBADDR1
address_b[1] => ram_block7a25.PORTBADDR1
address_b[1] => ram_block7a26.PORTBADDR1
address_b[1] => ram_block7a27.PORTBADDR1
address_b[1] => ram_block7a28.PORTBADDR1
address_b[1] => ram_block7a29.PORTBADDR1
address_b[1] => ram_block7a30.PORTBADDR1
address_b[1] => ram_block7a31.PORTBADDR1
address_b[1] => ram_block7a32.PORTBADDR1
address_b[2] => ram_block7a0.PORTBADDR2
address_b[2] => ram_block7a1.PORTBADDR2
address_b[2] => ram_block7a2.PORTBADDR2
address_b[2] => ram_block7a3.PORTBADDR2
address_b[2] => ram_block7a4.PORTBADDR2
address_b[2] => ram_block7a5.PORTBADDR2
address_b[2] => ram_block7a6.PORTBADDR2
address_b[2] => ram_block7a7.PORTBADDR2
address_b[2] => ram_block7a8.PORTBADDR2
address_b[2] => ram_block7a9.PORTBADDR2
address_b[2] => ram_block7a10.PORTBADDR2
address_b[2] => ram_block7a11.PORTBADDR2
address_b[2] => ram_block7a12.PORTBADDR2
address_b[2] => ram_block7a13.PORTBADDR2
address_b[2] => ram_block7a14.PORTBADDR2
address_b[2] => ram_block7a15.PORTBADDR2
address_b[2] => ram_block7a16.PORTBADDR2
address_b[2] => ram_block7a17.PORTBADDR2
address_b[2] => ram_block7a18.PORTBADDR2
address_b[2] => ram_block7a19.PORTBADDR2
address_b[2] => ram_block7a20.PORTBADDR2
address_b[2] => ram_block7a21.PORTBADDR2
address_b[2] => ram_block7a22.PORTBADDR2
address_b[2] => ram_block7a23.PORTBADDR2
address_b[2] => ram_block7a24.PORTBADDR2
address_b[2] => ram_block7a25.PORTBADDR2
address_b[2] => ram_block7a26.PORTBADDR2
address_b[2] => ram_block7a27.PORTBADDR2
address_b[2] => ram_block7a28.PORTBADDR2
address_b[2] => ram_block7a29.PORTBADDR2
address_b[2] => ram_block7a30.PORTBADDR2
address_b[2] => ram_block7a31.PORTBADDR2
address_b[2] => ram_block7a32.PORTBADDR2
address_b[3] => ram_block7a0.PORTBADDR3
address_b[3] => ram_block7a1.PORTBADDR3
address_b[3] => ram_block7a2.PORTBADDR3
address_b[3] => ram_block7a3.PORTBADDR3
address_b[3] => ram_block7a4.PORTBADDR3
address_b[3] => ram_block7a5.PORTBADDR3
address_b[3] => ram_block7a6.PORTBADDR3
address_b[3] => ram_block7a7.PORTBADDR3
address_b[3] => ram_block7a8.PORTBADDR3
address_b[3] => ram_block7a9.PORTBADDR3
address_b[3] => ram_block7a10.PORTBADDR3
address_b[3] => ram_block7a11.PORTBADDR3
address_b[3] => ram_block7a12.PORTBADDR3
address_b[3] => ram_block7a13.PORTBADDR3
address_b[3] => ram_block7a14.PORTBADDR3
address_b[3] => ram_block7a15.PORTBADDR3
address_b[3] => ram_block7a16.PORTBADDR3
address_b[3] => ram_block7a17.PORTBADDR3
address_b[3] => ram_block7a18.PORTBADDR3
address_b[3] => ram_block7a19.PORTBADDR3
address_b[3] => ram_block7a20.PORTBADDR3
address_b[3] => ram_block7a21.PORTBADDR3
address_b[3] => ram_block7a22.PORTBADDR3
address_b[3] => ram_block7a23.PORTBADDR3
address_b[3] => ram_block7a24.PORTBADDR3
address_b[3] => ram_block7a25.PORTBADDR3
address_b[3] => ram_block7a26.PORTBADDR3
address_b[3] => ram_block7a27.PORTBADDR3
address_b[3] => ram_block7a28.PORTBADDR3
address_b[3] => ram_block7a29.PORTBADDR3
address_b[3] => ram_block7a30.PORTBADDR3
address_b[3] => ram_block7a31.PORTBADDR3
address_b[3] => ram_block7a32.PORTBADDR3
address_b[4] => ram_block7a0.PORTBADDR4
address_b[4] => ram_block7a1.PORTBADDR4
address_b[4] => ram_block7a2.PORTBADDR4
address_b[4] => ram_block7a3.PORTBADDR4
address_b[4] => ram_block7a4.PORTBADDR4
address_b[4] => ram_block7a5.PORTBADDR4
address_b[4] => ram_block7a6.PORTBADDR4
address_b[4] => ram_block7a7.PORTBADDR4
address_b[4] => ram_block7a8.PORTBADDR4
address_b[4] => ram_block7a9.PORTBADDR4
address_b[4] => ram_block7a10.PORTBADDR4
address_b[4] => ram_block7a11.PORTBADDR4
address_b[4] => ram_block7a12.PORTBADDR4
address_b[4] => ram_block7a13.PORTBADDR4
address_b[4] => ram_block7a14.PORTBADDR4
address_b[4] => ram_block7a15.PORTBADDR4
address_b[4] => ram_block7a16.PORTBADDR4
address_b[4] => ram_block7a17.PORTBADDR4
address_b[4] => ram_block7a18.PORTBADDR4
address_b[4] => ram_block7a19.PORTBADDR4
address_b[4] => ram_block7a20.PORTBADDR4
address_b[4] => ram_block7a21.PORTBADDR4
address_b[4] => ram_block7a22.PORTBADDR4
address_b[4] => ram_block7a23.PORTBADDR4
address_b[4] => ram_block7a24.PORTBADDR4
address_b[4] => ram_block7a25.PORTBADDR4
address_b[4] => ram_block7a26.PORTBADDR4
address_b[4] => ram_block7a27.PORTBADDR4
address_b[4] => ram_block7a28.PORTBADDR4
address_b[4] => ram_block7a29.PORTBADDR4
address_b[4] => ram_block7a30.PORTBADDR4
address_b[4] => ram_block7a31.PORTBADDR4
address_b[4] => ram_block7a32.PORTBADDR4
address_b[5] => ram_block7a0.PORTBADDR5
address_b[5] => ram_block7a1.PORTBADDR5
address_b[5] => ram_block7a2.PORTBADDR5
address_b[5] => ram_block7a3.PORTBADDR5
address_b[5] => ram_block7a4.PORTBADDR5
address_b[5] => ram_block7a5.PORTBADDR5
address_b[5] => ram_block7a6.PORTBADDR5
address_b[5] => ram_block7a7.PORTBADDR5
address_b[5] => ram_block7a8.PORTBADDR5
address_b[5] => ram_block7a9.PORTBADDR5
address_b[5] => ram_block7a10.PORTBADDR5
address_b[5] => ram_block7a11.PORTBADDR5
address_b[5] => ram_block7a12.PORTBADDR5
address_b[5] => ram_block7a13.PORTBADDR5
address_b[5] => ram_block7a14.PORTBADDR5
address_b[5] => ram_block7a15.PORTBADDR5
address_b[5] => ram_block7a16.PORTBADDR5
address_b[5] => ram_block7a17.PORTBADDR5
address_b[5] => ram_block7a18.PORTBADDR5
address_b[5] => ram_block7a19.PORTBADDR5
address_b[5] => ram_block7a20.PORTBADDR5
address_b[5] => ram_block7a21.PORTBADDR5
address_b[5] => ram_block7a22.PORTBADDR5
address_b[5] => ram_block7a23.PORTBADDR5
address_b[5] => ram_block7a24.PORTBADDR5
address_b[5] => ram_block7a25.PORTBADDR5
address_b[5] => ram_block7a26.PORTBADDR5
address_b[5] => ram_block7a27.PORTBADDR5
address_b[5] => ram_block7a28.PORTBADDR5
address_b[5] => ram_block7a29.PORTBADDR5
address_b[5] => ram_block7a30.PORTBADDR5
address_b[5] => ram_block7a31.PORTBADDR5
address_b[5] => ram_block7a32.PORTBADDR5
address_b[6] => ram_block7a0.PORTBADDR6
address_b[6] => ram_block7a1.PORTBADDR6
address_b[6] => ram_block7a2.PORTBADDR6
address_b[6] => ram_block7a3.PORTBADDR6
address_b[6] => ram_block7a4.PORTBADDR6
address_b[6] => ram_block7a5.PORTBADDR6
address_b[6] => ram_block7a6.PORTBADDR6
address_b[6] => ram_block7a7.PORTBADDR6
address_b[6] => ram_block7a8.PORTBADDR6
address_b[6] => ram_block7a9.PORTBADDR6
address_b[6] => ram_block7a10.PORTBADDR6
address_b[6] => ram_block7a11.PORTBADDR6
address_b[6] => ram_block7a12.PORTBADDR6
address_b[6] => ram_block7a13.PORTBADDR6
address_b[6] => ram_block7a14.PORTBADDR6
address_b[6] => ram_block7a15.PORTBADDR6
address_b[6] => ram_block7a16.PORTBADDR6
address_b[6] => ram_block7a17.PORTBADDR6
address_b[6] => ram_block7a18.PORTBADDR6
address_b[6] => ram_block7a19.PORTBADDR6
address_b[6] => ram_block7a20.PORTBADDR6
address_b[6] => ram_block7a21.PORTBADDR6
address_b[6] => ram_block7a22.PORTBADDR6
address_b[6] => ram_block7a23.PORTBADDR6
address_b[6] => ram_block7a24.PORTBADDR6
address_b[6] => ram_block7a25.PORTBADDR6
address_b[6] => ram_block7a26.PORTBADDR6
address_b[6] => ram_block7a27.PORTBADDR6
address_b[6] => ram_block7a28.PORTBADDR6
address_b[6] => ram_block7a29.PORTBADDR6
address_b[6] => ram_block7a30.PORTBADDR6
address_b[6] => ram_block7a31.PORTBADDR6
address_b[6] => ram_block7a32.PORTBADDR6
clock0 => ram_block7a0.CLK0
clock0 => ram_block7a1.CLK0
clock0 => ram_block7a2.CLK0
clock0 => ram_block7a3.CLK0
clock0 => ram_block7a4.CLK0
clock0 => ram_block7a5.CLK0
clock0 => ram_block7a6.CLK0
clock0 => ram_block7a7.CLK0
clock0 => ram_block7a8.CLK0
clock0 => ram_block7a9.CLK0
clock0 => ram_block7a10.CLK0
clock0 => ram_block7a11.CLK0
clock0 => ram_block7a12.CLK0
clock0 => ram_block7a13.CLK0
clock0 => ram_block7a14.CLK0
clock0 => ram_block7a15.CLK0
clock0 => ram_block7a16.CLK0
clock0 => ram_block7a17.CLK0
clock0 => ram_block7a18.CLK0
clock0 => ram_block7a19.CLK0
clock0 => ram_block7a20.CLK0
clock0 => ram_block7a21.CLK0
clock0 => ram_block7a22.CLK0
clock0 => ram_block7a23.CLK0
clock0 => ram_block7a24.CLK0
clock0 => ram_block7a25.CLK0
clock0 => ram_block7a26.CLK0
clock0 => ram_block7a27.CLK0
clock0 => ram_block7a28.CLK0
clock0 => ram_block7a29.CLK0
clock0 => ram_block7a30.CLK0
clock0 => ram_block7a31.CLK0
clock0 => ram_block7a32.CLK0
clock1 => ram_block7a0.CLK1
clock1 => ram_block7a1.CLK1
clock1 => ram_block7a2.CLK1
clock1 => ram_block7a3.CLK1
clock1 => ram_block7a4.CLK1
clock1 => ram_block7a5.CLK1
clock1 => ram_block7a6.CLK1
clock1 => ram_block7a7.CLK1
clock1 => ram_block7a8.CLK1
clock1 => ram_block7a9.CLK1
clock1 => ram_block7a10.CLK1
clock1 => ram_block7a11.CLK1
clock1 => ram_block7a12.CLK1
clock1 => ram_block7a13.CLK1
clock1 => ram_block7a14.CLK1
clock1 => ram_block7a15.CLK1
clock1 => ram_block7a16.CLK1
clock1 => ram_block7a17.CLK1
clock1 => ram_block7a18.CLK1
clock1 => ram_block7a19.CLK1
clock1 => ram_block7a20.CLK1
clock1 => ram_block7a21.CLK1
clock1 => ram_block7a22.CLK1
clock1 => ram_block7a23.CLK1
clock1 => ram_block7a24.CLK1
clock1 => ram_block7a25.CLK1
clock1 => ram_block7a26.CLK1
clock1 => ram_block7a27.CLK1
clock1 => ram_block7a28.CLK1
clock1 => ram_block7a29.CLK1
clock1 => ram_block7a30.CLK1
clock1 => ram_block7a31.CLK1
clock1 => ram_block7a32.CLK1
clocken1 => ram_block7a0.ENA1
clocken1 => ram_block7a1.ENA1
clocken1 => ram_block7a2.ENA1
clocken1 => ram_block7a3.ENA1
clocken1 => ram_block7a4.ENA1
clocken1 => ram_block7a5.ENA1
clocken1 => ram_block7a6.ENA1
clocken1 => ram_block7a7.ENA1
clocken1 => ram_block7a8.ENA1
clocken1 => ram_block7a9.ENA1
clocken1 => ram_block7a10.ENA1
clocken1 => ram_block7a11.ENA1
clocken1 => ram_block7a12.ENA1
clocken1 => ram_block7a13.ENA1
clocken1 => ram_block7a14.ENA1
clocken1 => ram_block7a15.ENA1
clocken1 => ram_block7a16.ENA1
clocken1 => ram_block7a17.ENA1
clocken1 => ram_block7a18.ENA1
clocken1 => ram_block7a19.ENA1
clocken1 => ram_block7a20.ENA1
clocken1 => ram_block7a21.ENA1
clocken1 => ram_block7a22.ENA1
clocken1 => ram_block7a23.ENA1
clocken1 => ram_block7a24.ENA1
clocken1 => ram_block7a25.ENA1
clocken1 => ram_block7a26.ENA1
clocken1 => ram_block7a27.ENA1
clocken1 => ram_block7a28.ENA1
clocken1 => ram_block7a29.ENA1
clocken1 => ram_block7a30.ENA1
clocken1 => ram_block7a31.ENA1
clocken1 => ram_block7a32.ENA1
data_a[0] => ram_block7a0.PORTADATAIN
data_a[1] => ram_block7a1.PORTADATAIN
data_a[2] => ram_block7a2.PORTADATAIN
data_a[3] => ram_block7a3.PORTADATAIN
data_a[4] => ram_block7a4.PORTADATAIN
data_a[5] => ram_block7a5.PORTADATAIN
data_a[6] => ram_block7a6.PORTADATAIN
data_a[7] => ram_block7a7.PORTADATAIN
data_a[8] => ram_block7a8.PORTADATAIN
data_a[9] => ram_block7a9.PORTADATAIN
data_a[10] => ram_block7a10.PORTADATAIN
data_a[11] => ram_block7a11.PORTADATAIN
data_a[12] => ram_block7a12.PORTADATAIN
data_a[13] => ram_block7a13.PORTADATAIN
data_a[14] => ram_block7a14.PORTADATAIN
data_a[15] => ram_block7a15.PORTADATAIN
data_a[16] => ram_block7a16.PORTADATAIN
data_a[17] => ram_block7a17.PORTADATAIN
data_a[18] => ram_block7a18.PORTADATAIN
data_a[19] => ram_block7a19.PORTADATAIN
data_a[20] => ram_block7a20.PORTADATAIN
data_a[21] => ram_block7a21.PORTADATAIN
data_a[22] => ram_block7a22.PORTADATAIN
data_a[23] => ram_block7a23.PORTADATAIN
data_a[24] => ram_block7a24.PORTADATAIN
data_a[25] => ram_block7a25.PORTADATAIN
data_a[26] => ram_block7a26.PORTADATAIN
data_a[27] => ram_block7a27.PORTADATAIN
data_a[28] => ram_block7a28.PORTADATAIN
data_a[29] => ram_block7a29.PORTADATAIN
data_a[30] => ram_block7a30.PORTADATAIN
data_a[31] => ram_block7a31.PORTADATAIN
data_a[32] => ram_block7a32.PORTADATAIN
wren_a => ram_block7a0.PORTAWE
wren_a => ram_block7a0.ENA0
wren_a => ram_block7a1.PORTAWE
wren_a => ram_block7a1.ENA0
wren_a => ram_block7a2.PORTAWE
wren_a => ram_block7a2.ENA0
wren_a => ram_block7a3.PORTAWE
wren_a => ram_block7a3.ENA0
wren_a => ram_block7a4.PORTAWE
wren_a => ram_block7a4.ENA0
wren_a => ram_block7a5.PORTAWE
wren_a => ram_block7a5.ENA0
wren_a => ram_block7a6.PORTAWE
wren_a => ram_block7a6.ENA0
wren_a => ram_block7a7.PORTAWE
wren_a => ram_block7a7.ENA0
wren_a => ram_block7a8.PORTAWE
wren_a => ram_block7a8.ENA0
wren_a => ram_block7a9.PORTAWE
wren_a => ram_block7a9.ENA0
wren_a => ram_block7a10.PORTAWE
wren_a => ram_block7a10.ENA0
wren_a => ram_block7a11.PORTAWE
wren_a => ram_block7a11.ENA0
wren_a => ram_block7a12.PORTAWE
wren_a => ram_block7a12.ENA0
wren_a => ram_block7a13.PORTAWE
wren_a => ram_block7a13.ENA0
wren_a => ram_block7a14.PORTAWE
wren_a => ram_block7a14.ENA0
wren_a => ram_block7a15.PORTAWE
wren_a => ram_block7a15.ENA0
wren_a => ram_block7a16.PORTAWE
wren_a => ram_block7a16.ENA0
wren_a => ram_block7a17.PORTAWE
wren_a => ram_block7a17.ENA0
wren_a => ram_block7a18.PORTAWE
wren_a => ram_block7a18.ENA0
wren_a => ram_block7a19.PORTAWE
wren_a => ram_block7a19.ENA0
wren_a => ram_block7a20.PORTAWE
wren_a => ram_block7a20.ENA0
wren_a => ram_block7a21.PORTAWE
wren_a => ram_block7a21.ENA0
wren_a => ram_block7a22.PORTAWE
wren_a => ram_block7a22.ENA0
wren_a => ram_block7a23.PORTAWE
wren_a => ram_block7a23.ENA0
wren_a => ram_block7a24.PORTAWE
wren_a => ram_block7a24.ENA0
wren_a => ram_block7a25.PORTAWE
wren_a => ram_block7a25.ENA0
wren_a => ram_block7a26.PORTAWE
wren_a => ram_block7a26.ENA0
wren_a => ram_block7a27.PORTAWE
wren_a => ram_block7a27.ENA0
wren_a => ram_block7a28.PORTAWE
wren_a => ram_block7a28.ENA0
wren_a => ram_block7a29.PORTAWE
wren_a => ram_block7a29.ENA0
wren_a => ram_block7a30.PORTAWE
wren_a => ram_block7a30.ENA0
wren_a => ram_block7a31.PORTAWE
wren_a => ram_block7a31.ENA0
wren_a => ram_block7a32.PORTAWE
wren_a => ram_block7a32.ENA0