lp_rx_top_stratix.hier_info

altera fpga 和ts201的linkport接口设计

aclr => sub_parity4a1.IN0
aclr => sub_parity4a0.IN0
clock => counter5a[6].CLK
clock => counter5a[5].CLK
clock => counter5a[4].CLK
clock => counter5a[3].CLK
clock => counter5a[2].CLK
clock => counter5a[1].CLK
clock => counter5a[0].CLK
clock => parity3.CLK
clock => sub_parity4a0.CLK
clock => sub_parity4a1.CLK
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => cntr_cout[0].IN0
cnt_en => parity_cout.IN1


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:wrptr_g
aclr => counter5a[6].IN0
aclr => counter5a[5].IN0
aclr => counter5a[4].IN0
aclr => counter5a[3].IN0
aclr => counter5a[2].IN0
aclr => counter5a[1].IN0
aclr => counter5a[0].IN0
aclr => parity3.IN0
aclr => sub_parity4a1.IN0
aclr => sub_parity4a0.IN0
clock => counter5a[6].CLK
clock => counter5a[5].CLK
clock => counter5a[4].CLK
clock => counter5a[3].CLK
clock => counter5a[2].CLK
clock => counter5a[1].CLK
clock => counter5a[0].CLK
clock => parity3.CLK
clock => sub_parity4a0.CLK
clock => sub_parity4a1.CLK
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => _.IN0
cnt_en => cntr_cout[0].IN0
cnt_en => parity_cout.IN1


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dpram_1541:fiforam
data[0] => altsyncram_grh1:altsyncram6.data_a[0]
data[1] => altsyncram_grh1:altsyncram6.data_a[1]
data[2] => altsyncram_grh1:altsyncram6.data_a[2]
data[3] => altsyncram_grh1:altsyncram6.data_a[3]
data[4] => altsyncram_grh1:altsyncram6.data_a[4]
data[5] => altsyncram_grh1:altsyncram6.data_a[5]
data[6] => altsyncram_grh1:altsyncram6.data_a[6]
data[7] => altsyncram_grh1:altsyncram6.data_a[7]
data[8] => altsyncram_grh1:altsyncram6.data_a[8]
data[9] => altsyncram_grh1:altsyncram6.data_a[9]
data[10] => altsyncram_grh1:altsyncram6.data_a[10]
data[11] => altsyncram_grh1:altsyncram6.data_a[11]
data[12] => altsyncram_grh1:altsyncram6.data_a[12]
data[13] => altsyncram_grh1:altsyncram6.data_a[13]
data[14] => altsyncram_grh1:altsyncram6.data_a[14]
data[15] => altsyncram_grh1:altsyncram6.data_a[15]
data[16] => altsyncram_grh1:altsyncram6.data_a[16]
data[17] => altsyncram_grh1:altsyncram6.data_a[17]
data[18] => altsyncram_grh1:altsyncram6.data_a[18]
data[19] => altsyncram_grh1:altsyncram6.data_a[19]
data[20] => altsyncram_grh1:altsyncram6.data_a[20]
data[21] => altsyncram_grh1:altsyncram6.data_a[21]
data[22] => altsyncram_grh1:altsyncram6.data_a[22]
data[23] => altsyncram_grh1:altsyncram6.data_a[23]
data[24] => altsyncram_grh1:altsyncram6.data_a[24]
data[25] => altsyncram_grh1:altsyncram6.data_a[25]
data[26] => altsyncram_grh1:altsyncram6.data_a[26]
data[27] => altsyncram_grh1:altsyncram6.data_a[27]
data[28] => altsyncram_grh1:altsyncram6.data_a[28]
data[29] => altsyncram_grh1:altsyncram6.data_a[29]
data[30] => altsyncram_grh1:altsyncram6.data_a[30]
data[31] => altsyncram_grh1:altsyncram6.data_a[31]
data[32] => altsyncram_grh1:altsyncram6.data_a[32]
inclock => altsyncram_grh1:altsyncram6.clock0
outclock => altsyncram_grh1:altsyncram6.clock1
outclocken => altsyncram_grh1:altsyncram6.clocken1
rdaddress[0] => altsyncram_grh1:altsyncram6.address_b[0]
rdaddress[1] => altsyncram_grh1:altsyncram6.address_b[1]
rdaddress[2] => altsyncram_grh1:altsyncram6.address_b[2]
rdaddress[3] => altsyncram_grh1:altsyncram6.address_b[3]
rdaddress[4] => altsyncram_grh1:altsyncram6.address_b[4]
rdaddress[5] => altsyncram_grh1:altsyncram6.address_b[5]
rdaddress[6] => altsyncram_grh1:altsyncram6.address_b[6]
wraddress[0] => altsyncram_grh1:altsyncram6.address_a[0]
wraddress[1] => altsyncram_grh1:altsyncram6.address_a[1]
wraddress[2] => altsyncram_grh1:altsyncram6.address_a[2]
wraddress[3] => altsyncram_grh1:altsyncram6.address_a[3]
wraddress[4] => altsyncram_grh1:altsyncram6.address_a[4]
wraddress[5] => altsyncram_grh1:altsyncram6.address_a[5]
wraddress[6] => altsyncram_grh1:altsyncram6.address_a[6]
wren => altsyncram_grh1:altsyncram6.wren_a


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dpram_1541:fiforam|altsyncram_grh1:altsyncram6
address_a[0] => ram_block7a0.PORTAADDR
address_a[0] => ram_block7a1.PORTAADDR
address_a[0] => ram_block7a2.PORTAADDR
address_a[0] => ram_block7a3.PORTAADDR
address_a[0] => ram_block7a4.PORTAADDR
address_a[0] => ram_block7a5.PORTAADDR
address_a[0] => ram_block7a6.PORTAADDR
address_a[0] => ram_block7a7.PORTAADDR
address_a[0] => ram_block7a8.PORTAADDR
address_a[0] => ram_block7a9.PORTAADDR
address_a[0] => ram_block7a10.PORTAADDR
address_a[0] => ram_block7a11.PORTAADDR
address_a[0] => ram_block7a12.PORTAADDR
address_a[0] => ram_block7a13.PORTAADDR
address_a[0] => ram_block7a14.PORTAADDR
address_a[0] => ram_block7a15.PORTAADDR
address_a[0] => ram_block7a16.PORTAADDR
address_a[0] => ram_block7a17.PORTAADDR
address_a[0] => ram_block7a18.PORTAADDR
address_a[0] => ram_block7a19.PORTAADDR
address_a[0] => ram_block7a20.PORTAADDR
address_a[0] => ram_block7a21.PORTAADDR
address_a[0] => ram_block7a22.PORTAADDR
address_a[0] => ram_block7a23.PORTAADDR
address_a[0] => ram_block7a24.PORTAADDR
address_a[0] => ram_block7a25.PORTAADDR
address_a[0] => ram_block7a26.PORTAADDR
address_a[0] => ram_block7a27.PORTAADDR
address_a[0] => ram_block7a28.PORTAADDR
address_a[0] => ram_block7a29.PORTAADDR
address_a[0] => ram_block7a30.PORTAADDR
address_a[0] => ram_block7a31.PORTAADDR
address_a[0] => ram_block7a32.PORTAADDR
address_a[1] => ram_block7a0.PORTAADDR1
address_a[1] => ram_block7a1.PORTAADDR1
address_a[1] => ram_block7a2.PORTAADDR1
address_a[1] => ram_block7a3.PORTAADDR1
address_a[1] => ram_block7a4.PORTAADDR1
address_a[1] => ram_block7a5.PORTAADDR1
address_a[1] => ram_block7a6.PORTAADDR1
address_a[1] => ram_block7a7.PORTAADDR1
address_a[1] => ram_block7a8.PORTAADDR1
address_a[1] => ram_block7a9.PORTAADDR1
address_a[1] => ram_block7a10.PORTAADDR1
address_a[1] => ram_block7a11.PORTAADDR1
address_a[1] => ram_block7a12.PORTAADDR1
address_a[1] => ram_block7a13.PORTAADDR1
address_a[1] => ram_block7a14.PORTAADDR1
address_a[1] => ram_block7a15.PORTAADDR1
address_a[1] => ram_block7a16.PORTAADDR1
address_a[1] => ram_block7a17.PORTAADDR1
address_a[1] => ram_block7a18.PORTAADDR1
address_a[1] => ram_block7a19.PORTAADDR1
address_a[1] => ram_block7a20.PORTAADDR1
address_a[1] => ram_block7a21.PORTAADDR1
address_a[1] => ram_block7a22.PORTAADDR1
address_a[1] => ram_block7a23.PORTAADDR1
address_a[1] => ram_block7a24.PORTAADDR1
address_a[1] => ram_block7a25.PORTAADDR1
address_a[1] => ram_block7a26.PORTAADDR1
address_a[1] => ram_block7a27.PORTAADDR1
address_a[1] => ram_block7a28.PORTAADDR1
address_a[1] => ram_block7a29.PORTAADDR1
address_a[1] => ram_block7a30.PORTAADDR1
address_a[1] => ram_block7a31.PORTAADDR1
address_a[1] => ram_block7a32.PORTAADDR1
address_a[2] => ram_block7a0.PORTAADDR2
address_a[2] => ram_block7a1.PORTAADDR2
address_a[2] => ram_block7a2.PORTAADDR2
address_a[2] => ram_block7a3.PORTAADDR2
address_a[2] => ram_block7a4.PORTAADDR2
address_a[2] => ram_block7a5.PORTAADDR2
address_a[2] => ram_block7a6.PORTAADDR2
address_a[2] => ram_block7a7.PORTAADDR2
address_a[2] => ram_block7a8.PORTAADDR2
address_a[2] => ram_block7a9.PORTAADDR2
address_a[2] => ram_block7a10.PORTAADDR2
address_a[2] => ram_block7a11.PORTAADDR2
address_a[2] => ram_block7a12.PORTAADDR2
address_a[2] => ram_block7a13.PORTAADDR2
address_a[2] => ram_block7a14.PORTAADDR2
address_a[2] => ram_block7a15.PORTAADDR2
address_a[2] => ram_block7a16.PORTAADDR2
address_a[2] => ram_block7a17.PORTAADDR2
address_a[2] => ram_block7a18.PORTAADDR2
address_a[2] => ram_block7a19.PORTAADDR2
address_a[2] => ram_block7a20.PORTAADDR2
address_a[2] => ram_block7a21.PORTAADDR2
address_a[2] => ram_block7a22.PORTAADDR2
address_a[2] => ram_block7a23.PORTAADDR2
address_a[2] => ram_block7a24.PORTAADDR2
address_a[2] => ram_block7a25.PORTAADDR2
address_a[2] => ram_block7a26.PORTAADDR2
address_a[2] => ram_block7a27.PORTAADDR2
address_a[2] => ram_block7a28.PORTAADDR2
address_a[2] => ram_block7a29.PORTAADDR2
address_a[2] => ram_block7a30.PORTAADDR2
address_a[2] => ram_block7a31.PORTAADDR2
address_a[2] => ram_block7a32.PORTAADDR2
address_a[3] => ram_block7a0.PORTAADDR3
address_a[3] => ram_block7a1.PORTAADDR3
address_a[3] => ram_block7a2.PORTAADDR3
address_a[3] => ram_block7a3.PORTAADDR3
address_a[3] => ram_block7a4.PORTAADDR3
address_a[3] => ram_block7a5.PORTAADDR3
address_a[3] => ram_block7a6.PORTAADDR3
address_a[3] => ram_block7a7.PORTAADDR3
address_a[3] => ram_block7a8.PORTAADDR3
address_a[3] => ram_block7a9.PORTAADDR3
address_a[3] => ram_block7a10.PORTAADDR3
address_a[3] => ram_block7a11.PORTAADDR3
address_a[3] => ram_block7a12.PORTAADDR3
address_a[3] => ram_block7a13.PORTAADDR3
address_a[3] => ram_block7a14.PORTAADDR3
address_a[3] => ram_block7a15.PORTAADDR3
address_a[3] => ram_block7a16.PORTAADDR3
address_a[3] => ram_block7a17.PORTAADDR3
address_a[3] => ram_block7a18.PORTAADDR3
address_a[3] => ram_block7a19.PORTAADDR3
address_a[3] => ram_block7a20.PORTAADDR3
address_a[3] => ram_block7a21.PORTAADDR3
address_a[3] => ram_block7a22.PORTAADDR3
address_a[3] => ram_block7a23.PORTAADDR3
address_a[3] => ram_block7a24.PORTAADDR3
address_a[3] => ram_block7a25.PORTAADDR3
address_a[3] => ram_block7a26.PORTAADDR3
address_a[3] => ram_block7a27.PORTAADDR3
address_a[3] => ram_block7a28.PORTAADDR3
address_a[3] => ram_block7a29.PORTAADDR3
address_a[3] => ram_block7a30.PORTAADDR3
address_a[3] => ram_block7a31.PORTAADDR3
address_a[3] => ram_block7a32.PORTAADDR3
address_a[4] => ram_block7a0.PORTAADDR4
address_a[4] => ram_block7a1.PORTAADDR4
address_a[4] => ram_block7a2.PORTAADDR4
address_a[4] => ram_block7a3.PORTAADDR4
address_a[4] => ram_block7a4.PORTAADDR4
address_a[4] => ram_block7a5.PORTAADDR4
address_a[4] => ram_block7a6.PORTAADDR4
address_a[4] => ram_block7a7.PORTAADDR4
address_a[4] => ram_block7a8.PORTAADDR4
address_a[4] => ram_block7a9.PORTAADDR4
address_a[4] => ram_block7a10.PORTAADDR4
address_a[4] => ram_block7a11.PORTAADDR4
address_a[4] => ram_block7a12.PORTAADDR4
address_a[4] => ram_block7a13.PORTAADDR4
address_a[4] => ram_block7a14.PORTAADDR4
address_a[4] => ram_block7a15.PORTAADDR4
address_a[4] => ram_block7a16.PORTAADDR4
address_a[4] => ram_block7a17.PORTAADDR4
address_a[4] => ram_block7a18.PORTAADDR4
address_a[4] => ram_block7a19.PORTAADDR4
address_a[4] => ram_block7a20.PORTAADDR4
address_a[4] => ram_block7a21.PORTAADDR4
address_a[4] => ram_block7a22.PORTAADDR4
address_a[4] => ram_block7a23.PORTAADDR4
address_a[4] => ram_block7a24.PORTAADDR4
address_a[4] => ram_block7a25.PORTAADDR4
address_a[4] => ram_block7a26.PORTAADDR4
address_a[4] => ram_block7a27.PORTAADDR4
address_a[4] => ram_block7a28.PORTAADDR4
address_a[4] => ram_block7a29.PORTAADDR4
address_a[4] => ram_block7a30.PORTAADDR4
address_a[4] => ram_block7a31.PORTAADDR4
address_a[4] => ram_block7a32.PORTAADDR4
address_a[5] => ram_block7a0.PORTAADDR5
address_a[5] => ram_block7a1.PORTAADDR5
address_a[5] => ram_block7a2.PORTAADDR5
address_a[5] => ram_block7a3.PORTAADDR5
address_a[5] => ram_block7a4.PORTAADDR5
address_a[5] => ram_block7a5.PORTAADDR5
address_a[5] => ram_block7a6.PORTAADDR5
address_a[5] => ram_block7a7.PORTAADDR5
address_a[5] => ram_block7a8.PORTAADDR5
address_a[5] => ram_block7a9.PORTAADDR5
address_a[5] => ram_block7a10.PORTAADDR5
address_a[5] => ram_block7a11.PORTAADDR5
address_a[5] => ram_block7a12.PORTAADDR5
address_a[5] => ram_block7a13.PORTAADDR5
address_a[5] => ram_block7a14.PORTAADDR5
address_a[5] => ram_block7a15.PORTAADDR5
address_a[5] => ram_block7a16.PORTAADDR5
address_a[5] => ram_block7a17.PORTAADDR5
address_a[5] => ram_block7a18.PORTAADDR5
address_a[5] => ram_block7a19.PORTAADDR5
address_a[5] => ram_block7a20.PORTAADDR5
address_a[5] => ram_block7a21.PORTAADDR5
address_a[5] => ram_block7a22.PORTAADDR5
address_a[5] => ram_block7a23.PORTAADDR5
address_a[5] => ram_block7a24.PORTAADDR5
address_a[5] => ram_block7a25.PORTAADDR5
address_a[5] => ram_block7a26.PORTAADDR5
address_a[5] => ram_block7a27.PORTAADDR5
address_a[5] => ram_block7a28.PORTAADDR5
address_a[5] => ram_block7a29.PORTAADDR5
address_a[5] => ram_block7a30.PORTAADDR5
address_a[5] => ram_block7a31.PORTAADDR5
address_a[5] => ram_block7a32.PORTAADDR5
address_a[6] => ram_block7a0.PORTAADDR6
address_a[6] => ram_block7a1.PORTAADDR6
address_a[6] => ram_block7a2.PORTAADDR6
address_a[6] => ram_block7a3.PORTAADDR6
address_a[6] => ram_block7a4.PORTAADDR6
address_a[6] => ram_block7a5.PORTAADDR6
address_a[6] => ram_block7a6.PORTAADDR6
address_a[6] => ram_block7a7.PORTAADDR6
address_a[6] => ram_block7a8.PORTAADDR6
address_a[6] => ram_block7a9.PORTAADDR6
address_a[6] => ram_block7a10.PORTAADDR6
address_a[6] => ram_block7a11.PORTAADDR6
address_a[6] => ram_block7a12.PORTAADDR6
address_a[6] => ram_block7a13.PORTAADDR6
address_a[6] => ram_block7a14.PORTAADDR6
address_a[6] => ram_block7a15.PORTAADDR6
address_a[6] => ram_block7a16.PORTAADDR6
address_a[6] => ram_block7a17.PORTAADDR6
address_a[6] => ram_block7a18.PORTAADDR6
address_a[6] => ram_block7a19.PORTAADDR6
address_a[6] => ram_block7a20.PORTAADDR6
address_a[6] => ram_block7a21.PORTAADDR6
address_a[6] => ram_block7a22.PORTAADDR6
address_a[6] => ram_block7a23.PORTAADDR6
address_a[6] => ram_block7a24.PORTAADDR6
address_a[6] => ram_block7a25.PORTAADDR6
address_a[6] => ram_block7a26.PORTAADDR6
address_a[6] => ram_block7a27.PORTAADDR6
address_a[6] => ram_block7a28.PORTAADDR6
address_a[6] => ram_block7a29.PORTAADDR6
address_a[6] => ram_block7a30.PORTAADDR6
address_a[6] => ram_block7a31.PORTAADDR6
address_a[6] => ram_block7a32.PORTAADDR6
address_b[0] => ram_block7a0.PORTBADDR
address_b[0] => ram_block7a1.PORTBADDR
address_b[0] => ram_block7a2.PORTBADDR
address_b[0] => ram_block7a3.PORTBADDR
address_b[0] => ram_block7a4.PORTBADDR
address_b[0] => ram_block7a5.PORTBADDR
address_b[0] => ram_block7a6.PORTBADDR
address_b[0] => ram_block7a7.PORTBADDR
address_b[0] => ram_block7a8.PORTBADDR
address_b[0] => ram_block7a9.PORTBADDR
address_b[0] => ram_block7a10.PORTBADDR
address_b[0] => ram_block7a11.PORTBADDR
address_b[0] => ram_block7a12.PORTBADDR
address_b[0] => ram_block7a13.PORTBADDR
address_b[0] => ram_block7a14.PORTBADDR
address_b[0] => ram_block7a15.PORTBADDR
address_b[0] => ram_block7a16.PORTBADDR
address_b[0] => ram_block7a17.PORTBADDR
address_b[0] => ram_block7a18.PORTBADDR
address_b[0] => ram_block7a19.PORTBADDR
address_b[0] => ram_block7a20.PORTBADDR
address_b[0] => ram_block7a21.PORTBADDR
address_b[0] => ram_block7a22.PORTBADDR
address_b[0] => ram_block7a23.PORTBADDR
address_b[0] => ram_block7a24.PORTBADDR
address_b[0] => ram_block7a25.PORTBADDR
address_b[0] => ram_block7a26.PORTBADDR
address_b[0] => ram_block7a27.PORTBADDR
address_b[0] => ram_block7a28.PORTBADDR
address_b[0] => ram_block7a29.PORTBADDR
address_b[0] => ram_block7a30.PORTBADDR
address_b[0] => ram_block7a31.PORTBADDR
address_b[0] => ram_block7a32.PORTBADDR
address_b[1] => ram_block7a0.PORTBADDR1
address_b[1] => ram_block7a1.PORTBADDR1
address_b[1] => ram_block7a2.PORTBADDR1
address_b[1] => ram_block7a3.PORTBADDR1
address_b[1] => ram_block7a4.PORTBADDR1
address_b[1] => ram_block7a5.PORTBADDR1
address_b[1] => ram_block7a6.PORTBADDR1
address_b[1] => ram_block7a7.PORTBADDR1
address_b[1] => ram_block7a8.PORTBADDR1
address_b[1] => ram_block7a9.PORTBADDR1