lp_rx_top_stratix.hier_info

altera fpga 和ts201的linkport接口设计

|lp_rx_top_stratix
clk => clk.IN1
rst_n => rst_n.IN1
datain[0] => datain[0].IN1
datain[1] => datain[1].IN1
datain[2] => datain[2].IN1
datain[3] => datain[3].IN1
inclock => inclock.IN1
inclock_en => inclock_en.IN1
rvere => rvere.IN1
bcmpi_n => bcmpi_n.IN1
rdreq => rdreq.IN1


|lp_rx_top_stratix|lp_rx:lp_rx
clk => clk.IN2
rst_n => _.IN1
rst_n => datain_pos[0].ACLR
rst_n => datain_pos[1].ACLR
rst_n => datain_pos[2].ACLR
rst_n => datain_pos[3].ACLR
rst_n => datain_pos[4].ACLR
rst_n => datain_pos[5].ACLR
rst_n => datain_pos[6].ACLR
rst_n => datain_pos[7].ACLR
rst_n => datain_pos[8].ACLR
rst_n => datain_pos[9].ACLR
rst_n => datain_pos[10].ACLR
rst_n => datain_pos[11].ACLR
rst_n => acko~reg0.PRESET
rst_n => rcser~reg0.ACLR
rst_n => datain_neg[0].ACLR
rst_n => datain_neg[1].ACLR
rst_n => datain_neg[2].ACLR
rst_n => datain_neg[3].ACLR
rst_n => datain_neg[4].ACLR
rst_n => datain_neg[5].ACLR
rst_n => datain_neg[6].ACLR
rst_n => datain_neg[7].ACLR
rst_n => datain_neg[8].ACLR
rst_n => datain_neg[9].ACLR
rst_n => datain_neg[10].ACLR
rst_n => datain_neg[11].ACLR
rst_n => pos_edges[0].ACLR
rst_n => pos_edges[1].ACLR
rst_n => pos_edges[2].ACLR
rst_n => pos_edges[3].ACLR
rst_n => pos_edges[4].ACLR
rst_n => neg_edges[0].ACLR
rst_n => neg_edges[1].ACLR
rst_n => neg_edges[2].ACLR
rst_n => neg_edges[3].ACLR
rst_n => neg_edges[4].ACLR
rst_n => data_ready.ACLR
rst_n => dr_sync2.ACLR
rst_n => dr_sync1.ACLR
rst_n => fifo_wdata[0].ACLR
rst_n => fifo_wdata[1].ACLR
rst_n => fifo_wdata[2].ACLR
rst_n => fifo_wdata[3].ACLR
rst_n => fifo_wdata[4].ACLR
rst_n => fifo_wdata[5].ACLR
rst_n => fifo_wdata[6].ACLR
rst_n => fifo_wdata[7].ACLR
rst_n => fifo_wdata[8].ACLR
rst_n => fifo_wdata[9].ACLR
rst_n => fifo_wdata[10].ACLR
rst_n => fifo_wdata[11].ACLR
rst_n => fifo_wdata[12].ACLR
rst_n => fifo_wdata[13].ACLR
rst_n => fifo_wdata[14].ACLR
rst_n => fifo_wdata[15].ACLR
rst_n => fifo_wdata[16].ACLR
rst_n => fifo_wdata[17].ACLR
rst_n => fifo_wdata[18].ACLR
rst_n => fifo_wdata[19].ACLR
rst_n => fifo_wdata[20].ACLR
rst_n => fifo_wdata[21].ACLR
rst_n => fifo_wdata[22].ACLR
rst_n => fifo_wdata[23].ACLR
rst_n => fifo_wdata[24].ACLR
rst_n => fifo_wdata[25].ACLR
rst_n => fifo_wdata[26].ACLR
rst_n => fifo_wdata[27].ACLR
rst_n => fifo_wdata[28].ACLR
rst_n => fifo_wdata[29].ACLR
rst_n => fifo_wdata[30].ACLR
rst_n => fifo_wdata[31].ACLR
rst_n => fifo_wdata[32].ACLR
rst_n => fifo_we.ACLR
rst_n => load_ver_l.ACLR
rst_n => load_ver_h.ACLR
rst_n => ver_l[0].ACLR
rst_n => ver_l[1].ACLR
rst_n => ver_l[2].ACLR
rst_n => ver_l[3].ACLR
rst_n => ver_h[0].ACLR
rst_n => ver_h[1].ACLR
rst_n => ver_h[2].ACLR
rst_n => ver_h[3].ACLR
rst_n => words[0].ACLR
rst_n => words[1].ACLR
rst_n => pos_chk_en.ACLR
rst_n => neg_chk_en.ACLR
rst_n => low_nibble_chk[0].ACLR
rst_n => low_nibble_chk[1].ACLR
rst_n => low_nibble_chk[2].ACLR
rst_n => low_nibble_chk[3].ACLR
rst_n => low_nibble_chk[4].ACLR
rst_n => mid_nibble_chk[0].ACLR
rst_n => mid_nibble_chk[1].ACLR
rst_n => mid_nibble_chk[2].ACLR
rst_n => mid_nibble_chk[3].ACLR
rst_n => low_nibble_chk_r[0].ACLR
rst_n => low_nibble_chk_r[1].ACLR
rst_n => low_nibble_chk_r[2].ACLR
rst_n => low_nibble_chk_r[3].ACLR
rst_n => low_nibble_chk_r[4].ACLR
rst_n => low_nibble_chk_r[5].ACLR
rst_n => low_nibble_chk_r[6].ACLR
rst_n => low_nibble_chk_r[7].ACLR
rst_n => high_nibble_chk[0].ACLR
rst_n => high_nibble_chk[1].ACLR
rst_n => high_nibble_chk[2].ACLR
rst_n => high_nibble_chk[3].ACLR
rst_n => high_nibble_chk_r[0].ACLR
rst_n => high_nibble_chk_r[1].ACLR
rst_n => high_nibble_chk_r[2].ACLR
rst_n => high_nibble_chk_r[3].ACLR
rst_n => bcmp.ACLR
rst_n => bcmpi_sync_n.PRESET
rst_n => blk_end.ACLR
rst_n => sample_bcmp.ACLR
datain[0] => datain_neg[8].DATAIN
datain[0] => datain_pos[8].DATAIN
datain[0] => neg_data[12].DATAIN
datain[0] => pos_data[12].DATAIN
datain[1] => datain_neg[9].DATAIN
datain[1] => datain_pos[9].DATAIN
datain[1] => neg_data[13].DATAIN
datain[1] => pos_data[13].DATAIN
datain[2] => datain_neg[10].DATAIN
datain[2] => datain_pos[10].DATAIN
datain[2] => neg_data[14].DATAIN
datain[2] => pos_data[14].DATAIN
datain[3] => datain_neg[11].DATAIN
datain[3] => datain_pos[11].DATAIN
datain[3] => neg_data[15].DATAIN
datain[3] => pos_data[15].DATAIN
inclock => inclock_gated.IN0
inclock_en => inclock_gated.IN1
bcmpi_n => bcmpi_sync_n.DATAIN
rvere => pos_edges.OUTPUTSELECT
rvere => pos_edges.OUTPUTSELECT
rvere => pos_edges.OUTPUTSELECT
rvere => pos_edges.OUTPUTSELECT
rvere => Selector4.IN4
rvere => Selector5.IN5
rdreq => rdreq.IN1


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo
data[0] => dcfifo_0pm1:auto_generated.data[0]
data[1] => dcfifo_0pm1:auto_generated.data[1]
data[2] => dcfifo_0pm1:auto_generated.data[2]
data[3] => dcfifo_0pm1:auto_generated.data[3]
data[4] => dcfifo_0pm1:auto_generated.data[4]
data[5] => dcfifo_0pm1:auto_generated.data[5]
data[6] => dcfifo_0pm1:auto_generated.data[6]
data[7] => dcfifo_0pm1:auto_generated.data[7]
data[8] => dcfifo_0pm1:auto_generated.data[8]
data[9] => dcfifo_0pm1:auto_generated.data[9]
data[10] => dcfifo_0pm1:auto_generated.data[10]
data[11] => dcfifo_0pm1:auto_generated.data[11]
data[12] => dcfifo_0pm1:auto_generated.data[12]
data[13] => dcfifo_0pm1:auto_generated.data[13]
data[14] => dcfifo_0pm1:auto_generated.data[14]
data[15] => dcfifo_0pm1:auto_generated.data[15]
data[16] => dcfifo_0pm1:auto_generated.data[16]
data[17] => dcfifo_0pm1:auto_generated.data[17]
data[18] => dcfifo_0pm1:auto_generated.data[18]
data[19] => dcfifo_0pm1:auto_generated.data[19]
data[20] => dcfifo_0pm1:auto_generated.data[20]
data[21] => dcfifo_0pm1:auto_generated.data[21]
data[22] => dcfifo_0pm1:auto_generated.data[22]
data[23] => dcfifo_0pm1:auto_generated.data[23]
data[24] => dcfifo_0pm1:auto_generated.data[24]
data[25] => dcfifo_0pm1:auto_generated.data[25]
data[26] => dcfifo_0pm1:auto_generated.data[26]
data[27] => dcfifo_0pm1:auto_generated.data[27]
data[28] => dcfifo_0pm1:auto_generated.data[28]
data[29] => dcfifo_0pm1:auto_generated.data[29]
data[30] => dcfifo_0pm1:auto_generated.data[30]
data[31] => dcfifo_0pm1:auto_generated.data[31]
data[32] => dcfifo_0pm1:auto_generated.data[32]
rdclk => dcfifo_0pm1:auto_generated.rdclk
rdreq => dcfifo_0pm1:auto_generated.rdreq
wrclk => dcfifo_0pm1:auto_generated.wrclk
wrreq => dcfifo_0pm1:auto_generated.wrreq
aclr => dcfifo_0pm1:auto_generated.aclr


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated
aclr => a_fefifo_qec:read_state.aclr
aclr => a_fefifo_3bc:write_state.aclr
aclr => a_graycounter_u16:rdptr_g.aclr
aclr => a_graycounter_u16:wrptr_g.aclr
aclr => write_delay_cycle[6].IN0
aclr => cntr_cua:rdptr_b.aclr
aclr => cntr_cua:wrptr_b.aclr
aclr => tmp_aclr.IN0
data[0] => dpram_1541:fiforam.data[0]
data[1] => dpram_1541:fiforam.data[1]
data[2] => dpram_1541:fiforam.data[2]
data[3] => dpram_1541:fiforam.data[3]
data[4] => dpram_1541:fiforam.data[4]
data[5] => dpram_1541:fiforam.data[5]
data[6] => dpram_1541:fiforam.data[6]
data[7] => dpram_1541:fiforam.data[7]
data[8] => dpram_1541:fiforam.data[8]
data[9] => dpram_1541:fiforam.data[9]
data[10] => dpram_1541:fiforam.data[10]
data[11] => dpram_1541:fiforam.data[11]
data[12] => dpram_1541:fiforam.data[12]
data[13] => dpram_1541:fiforam.data[13]
data[14] => dpram_1541:fiforam.data[14]
data[15] => dpram_1541:fiforam.data[15]
data[16] => dpram_1541:fiforam.data[16]
data[17] => dpram_1541:fiforam.data[17]
data[18] => dpram_1541:fiforam.data[18]
data[19] => dpram_1541:fiforam.data[19]
data[20] => dpram_1541:fiforam.data[20]
data[21] => dpram_1541:fiforam.data[21]
data[22] => dpram_1541:fiforam.data[22]
data[23] => dpram_1541:fiforam.data[23]
data[24] => dpram_1541:fiforam.data[24]
data[25] => dpram_1541:fiforam.data[25]
data[26] => dpram_1541:fiforam.data[26]
data[27] => dpram_1541:fiforam.data[27]
data[28] => dpram_1541:fiforam.data[28]
data[29] => dpram_1541:fiforam.data[29]
data[30] => dpram_1541:fiforam.data[30]
data[31] => dpram_1541:fiforam.data[31]
data[32] => dpram_1541:fiforam.data[32]
rdclk => a_fefifo_qec:read_state.clock
rdclk => a_graycounter_u16:rdptr_g.clock
rdclk => dpram_1541:fiforam.outclock
rdclk => dffpipe_ed9:dffpipe_rdbuw.clock
rdclk => dffpipe_ed9:dffpipe_rdusedw.clock
rdclk => dffpipe_ed9:dffpipe_rs_dbwp.clock
rdclk => alt_synch_pipe_mc8:dffpipe_rs_dgwp.clock
rdclk => cntr_cua:rdptr_b.clock
rdreq => a_fefifo_qec:read_state.rreq
rdreq => valid_rreq.IN0
wrclk => a_fefifo_3bc:write_state.clock
wrclk => a_graycounter_u16:wrptr_g.clock
wrclk => dpram_1541:fiforam.inclock
wrclk => dffpipe_ed9:dffpipe_wr_dbuw.clock
wrclk => dffpipe_ed9:dffpipe_wrusedw.clock
wrclk => alt_synch_pipe_mc8:dffpipe_ws_dgrp.clock
wrclk => dffpipe_ed9:dffpipe_ws_nbrp.clock
wrclk => cntr_cua:wrptr_b.clock
wrclk => write_delay_cycle[6].CLK
wrclk => write_delay_cycle[5].CLK
wrclk => write_delay_cycle[4].CLK
wrclk => write_delay_cycle[3].CLK
wrclk => write_delay_cycle[2].CLK
wrclk => write_delay_cycle[1].CLK
wrclk => write_delay_cycle[0].CLK
wrreq => a_fefifo_3bc:write_state.wreq
wrreq => valid_wreq.IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_fefifo_qec:read_state
aclr => b_full.IN0
aclr => b_non_empty.IN0
aclr => b_one.IN0
aclr => llreq.IN0
clock => b_full.CLK
clock => b_non_empty.CLK
clock => b_one.CLK
clock => llreq.CLK
rreq => _.IN1
rreq => _.IN1
rreq => llreq.IN0
usedw_in[0] => is_one0.IN0
usedw_in[0] => is_two0.IN0
usedw_in[0] => is_zero0.IN0
usedw_in[0] => _.IN0
usedw_in[0] => op_1.IN14
usedw_in[1] => is_one1.IN0
usedw_in[1] => is_two1.IN0
usedw_in[1] => is_zero1.IN0
usedw_in[1] => _.IN0
usedw_in[1] => op_1.IN12
usedw_in[2] => is_one2.IN0
usedw_in[2] => is_two2.IN0
usedw_in[2] => is_zero2.IN0
usedw_in[2] => _.IN0
usedw_in[2] => op_1.IN10
usedw_in[3] => is_one3.IN0
usedw_in[3] => is_two3.IN0
usedw_in[3] => is_zero3.IN0
usedw_in[3] => _.IN0
usedw_in[3] => op_1.IN8
usedw_in[4] => is_one4.IN0
usedw_in[4] => is_two4.IN0
usedw_in[4] => is_zero4.IN0
usedw_in[4] => _.IN0
usedw_in[4] => op_1.IN6
usedw_in[5] => is_one5.IN0
usedw_in[5] => is_two5.IN0
usedw_in[5] => is_zero5.IN0
usedw_in[5] => _.IN0
usedw_in[5] => op_1.IN4
usedw_in[6] => is_one6.IN0
usedw_in[6] => is_two6.IN0
usedw_in[6] => is_zero6.IN0
usedw_in[6] => _.IN0
usedw_in[6] => op_1.IN2


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_fefifo_3bc:write_state
aclr => b_full.IN0
aclr => b_non_empty.IN0
aclr => b_one.IN0
clock => b_full.CLK
clock => b_non_empty.CLK
clock => b_one.CLK
usedw_in[0] => is_zero0.IN0
usedw_in[0] => _.IN0
usedw_in[0] => op_1.IN14
usedw_in[1] => is_zero1.IN0
usedw_in[1] => _.IN0
usedw_in[1] => op_1.IN12
usedw_in[2] => is_zero2.IN0
usedw_in[2] => _.IN0
usedw_in[2] => op_1.IN10
usedw_in[3] => is_zero3.IN0
usedw_in[3] => _.IN0
usedw_in[3] => op_1.IN8
usedw_in[4] => is_zero4.IN0
usedw_in[4] => _.IN0
usedw_in[4] => op_1.IN6
usedw_in[5] => is_zero5.IN0
usedw_in[5] => _.IN0
usedw_in[5] => op_1.IN4
usedw_in[6] => is_zero6.IN0
usedw_in[6] => _.IN0
usedw_in[6] => op_1.IN2
wreq => b_non_empty.IN0
wreq => _.IN0
wreq => _.IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_gray2bin_l5b:gray2bin_rs_nbwp
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN1
gray[6] => bin[6].DATAIN
gray[6] => xor5.IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_gray2bin_l5b:gray2bin_ws_nbrp
gray[0] => xor0.IN0
gray[1] => xor1.IN0
gray[2] => xor2.IN0
gray[3] => xor3.IN0
gray[4] => xor4.IN0
gray[5] => xor5.IN1
gray[6] => bin[6].DATAIN
gray[6] => xor5.IN0


|lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:rdptr_g
aclr => counter5a[6].IN0
aclr => counter5a[5].IN0
aclr => counter5a[4].IN0
aclr => counter5a[3].IN0
aclr => counter5a[2].IN0
aclr => counter5a[1].IN0
aclr => counter5a[0].IN0
aclr => parity3.IN0