lp_rx_top_stratix.map.rpt

altera fpga 和ts201的linkport接口设计

; LPM_WIDTH               ; 33          ; Signed Integer                  ;
; LPM_NUMWORDS            ; 128         ; Signed Integer                  ;
; LPM_WIDTHU              ; 7           ; Signed Integer                  ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                         ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                         ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                         ;
; USE_EAB                 ; ON          ; Untyped                         ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                         ;
; DELAY_RDUSEDW           ; 1           ; Untyped                         ;
; DELAY_WRUSEDW           ; 1           ; Untyped                         ;
; RDSYNC_DELAYPIPE        ; 3           ; Untyped                         ;
; WRSYNC_DELAYPIPE        ; 3           ; Untyped                         ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                         ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                         ;
; DEVICE_FAMILY           ; Stratix     ; Untyped                         ;
; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                         ;
; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                         ;
; READ_ACLR_SYNCH         ; OFF         ; Untyped                         ;
; CBXI_PARAMETER          ; dcfifo_0pm1 ; Untyped                         ;
+-------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance            ;
+----------------------------+----------------------------+
; Name                       ; Value                      ;
+----------------------------+----------------------------+
; Number of entity instances ; 1                          ;
; Entity Instance            ; lp_rx:lp_rx|dcfifo:rx_fifo ;
;     -- FIFO Type           ; Dual Clock                 ;
;     -- LPM_WIDTH           ; 33                         ;
;     -- LPM_NUMWORDS        ; 128                        ;
;     -- LPM_SHOWAHEAD       ; OFF                        ;
;     -- USE_EAB             ; ON                         ;
+----------------------------+----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:01     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 11.1 Build 173 11/01/2011 SJ Full Version
    Info: Processing started: Fri Apr 06 19:27:25 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lp_rx_top_stratix -c lp_rx_top_stratix
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file /fpga_test/ts201_altera/link_port-v1.1.0/source/verilog/lp_rx.v
    Info (12023): Found entity 1: lp_rx
Warning (12125): Using design file lp_rx_top_stratix.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info (12023): Found entity 1: lp_rx_top_stratix
Info (12127): Elaborating entity "lp_rx_top_stratix" for the top level hierarchy
Info (12128): Elaborating entity "lp_rx" for hierarchy "lp_rx:lp_rx"
Warning (10036): Verilog HDL or VHDL warning at lp_rx.v(201): object "dr_sync4" assigned a value but never read
Info (12128): Elaborating entity "dcfifo" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo"
Info (12130): Elaborated megafunction instantiation "lp_rx:lp_rx|dcfifo:rx_fifo"
Info (12133): Instantiated megafunction "lp_rx:lp_rx|dcfifo:rx_fifo" with the following parameter:
    Info (12134): Parameter "intended_device_family" = "Stratix"
    Info (12134): Parameter "lpm_width" = "33"
    Info (12134): Parameter "lpm_numwords" = "128"
    Info (12134): Parameter "lpm_widthu" = "7"
    Info (12134): Parameter "clocks_are_synchronized" = "FALSE"
    Info (12134): Parameter "lpm_type" = "dcfifo"
    Info (12134): Parameter "lpm_showahead" = "OFF"
    Info (12134): Parameter "overflow_checking" = "ON"
    Info (12134): Parameter "underflow_checking" = "ON"
    Info (12134): Parameter "use_eab" = "ON"
    Info (12134): Parameter "add_ram_output_register" = "OFF"
    Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO"
Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_0pm1.tdf
    Info (12023): Found entity 1: dcfifo_0pm1
Info (12128): Elaborating entity "dcfifo_0pm1" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_qec.tdf
    Info (12023): Found entity 1: a_fefifo_qec
Info (12128): Elaborating entity "a_fefifo_qec" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_fefifo_qec:read_state"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_3bc.tdf
    Info (12023): Found entity 1: a_fefifo_3bc
Info (12128): Elaborating entity "a_fefifo_3bc" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_fefifo_3bc:write_state"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_l5b.tdf
    Info (12023): Found entity 1: a_gray2bin_l5b
Info (12128): Elaborating entity "a_gray2bin_l5b" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_gray2bin_l5b:gray2bin_rs_nbwp"
Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_u16.tdf
    Info (12023): Found entity 1: a_graycounter_u16
Info (12128): Elaborating entity "a_graycounter_u16" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:rdptr_g"
Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_1541.tdf
    Info (12023): Found entity 1: dpram_1541
Info (12128): Elaborating entity "dpram_1541" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dpram_1541:fiforam"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_grh1.tdf
    Info (12023): Found entity 1: altsyncram_grh1
Info (12128): Elaborating entity "altsyncram_grh1" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dpram_1541:fiforam|altsyncram_grh1:altsyncram6"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ed9.tdf
    Info (12023): Found entity 1: dffpipe_ed9
Info (12128): Elaborating entity "dffpipe_ed9" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rdbuw"
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_mc8.tdf
    Info (12023): Found entity 1: alt_synch_pipe_mc8
Info (12128): Elaborating entity "alt_synch_pipe_mc8" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp"
Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf
    Info (12023): Found entity 1: dffpipe_gd9
Info (12128): Elaborating entity "dffpipe_gd9" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp|dffpipe_gd9:dffpipe9"
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_bvb.tdf
    Info (12023): Found entity 1: add_sub_bvb
Info (12128): Elaborating entity "add_sub_bvb" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|add_sub_bvb:lpm_add_sub_rd_udwn"
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cua.tdf
    Info (12023): Found entity 1: cntr_cua
Info (12128): Elaborating entity "cntr_cua" for hierarchy "lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|cntr_cua:rdptr_b"
Info (13005): Duplicate registers merged to single register
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "speed" technology mapper which leaves 14 WYSIWYG logic cells and I/Os untouched
Info (18000): Registers with preset signals will power-up high
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (15717): Design contains 37 virtual pins; timing numbers associated with paths containing virtual pins are estimates
    Info (15719): Pin "rcser" is virtual output pin
    Info (15719): Pin "empty" is virtual output pin
    Info (15719): Pin "rdata[0]" is virtual output pin
    Info (15719): Pin "rdata[1]" is virtual output pin
    Info (15719): Pin "rdata[2]" is virtual output pin
    Info (15719): Pin "rdata[3]" is virtual output pin
    Info (15719): Pin "rdata[4]" is virtual output pin