📄 lp_rx_top_stratix.map.rpt
字号:
+--------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
; |lp_rx_top_stratix ; 307 (0) ; 265 ; 4224 ; 0 ; 0 ; 0 ; 0 ; 10 ; 37 ; 42 (0) ; 166 (0) ; 99 (0) ; 46 (0) ; 0 (0) ; |lp_rx_top_stratix ; ;
; |lp_rx:lp_rx| ; 307 (177) ; 265 ; 4224 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (27) ; 166 (112) ; 99 (38) ; 46 (18) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx ; ;
; |dcfifo:rx_fifo| ; 130 (0) ; 115 ; 4224 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 (0) ; 54 (0) ; 61 (0) ; 28 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo ; ;
; |dcfifo_0pm1:auto_generated| ; 130 (9) ; 115 ; 4224 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 (2) ; 54 (7) ; 61 (0) ; 28 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated ; ;
; |a_fefifo_3bc:write_state| ; 3 (3) ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_fefifo_3bc:write_state ; ;
; |a_fefifo_qec:read_state| ; 8 (8) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 1 (1) ; 2 (2) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_fefifo_qec:read_state ; ;
; |a_gray2bin_l5b:gray2bin_rs_nbwp| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_gray2bin_l5b:gray2bin_rs_nbwp ; ;
; |a_gray2bin_l5b:gray2bin_ws_nbrp| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_gray2bin_l5b:gray2bin_ws_nbrp ; ;
; |a_graycounter_u16:rdptr_g| ; 12 (12) ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:rdptr_g ; ;
; |a_graycounter_u16:wrptr_g| ; 12 (12) ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:wrptr_g ; ;
; |alt_synch_pipe_mc8:dffpipe_rs_dgwp| ; 21 (0) ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 21 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp ; ;
; |dffpipe_gd9:dffpipe9| ; 21 (21) ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 21 (21) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp|dffpipe_gd9:dffpipe9 ; ;
; |alt_synch_pipe_mc8:dffpipe_ws_dgrp| ; 21 (0) ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 21 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_ws_dgrp ; ;
; |dffpipe_gd9:dffpipe9| ; 21 (21) ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 21 (21) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_ws_dgrp|dffpipe_gd9:dffpipe9 ; ;
; |cntr_cua:rdptr_b| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 7 (7) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|cntr_cua:rdptr_b ; ;
; |cntr_cua:wrptr_b| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 7 (7) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|cntr_cua:wrptr_b ; ;
; |dffpipe_ed9:dffpipe_rdbuw| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 7 (7) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rdbuw ; ;
; |dffpipe_ed9:dffpipe_rs_dbwp| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 5 (5) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rs_dbwp ; ;
; |dffpipe_ed9:dffpipe_wrusedw| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 7 (7) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw ; ;
; |dffpipe_ed9:dffpipe_ws_nbrp| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 5 (5) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_ws_nbrp ; ;
; |dpram_1541:fiforam| ; 0 (0) ; 0 ; 4224 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dpram_1541:fiforam ; ;
; |altsyncram_grh1:altsyncram6| ; 0 (0) ; 0 ; 4224 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_rx_top_stratix|lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dpram_1541:fiforam|altsyncram_grh1:altsyncram6 ; ;
+--------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-----------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-----------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dpram_1541:fiforam|altsyncram_grh1:altsyncram6|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 33 ; 128 ; 33 ; 4224 ; None ;
+-----------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw|dffe8a[6] ; Merged with lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw|dffe8a[6] ;
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw|dffe8a[5] ; Merged with lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw|dffe8a[5] ;
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw|dffe8a[4] ; Merged with lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw|dffe8a[4] ;
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw|dffe8a[3] ; Merged with lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw|dffe8a[3] ;
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw|dffe8a[2] ; Merged with lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw|dffe8a[2] ;
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw|dffe8a[1] ; Merged with lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw|dffe8a[1] ;
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw|dffe8a[0] ; Merged with lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw|dffe8a[0] ;
; Total Number of Removed Registers = 7 ; ;
+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 265 ;
; Number of registers using Synchronous Clear ; 9 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 231 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 93 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------------------------------------------------------------+---------+
; lp_rx:lp_rx|acko ; 1 ;
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:wrptr_g|sub_parity4a0 ; 1 ;
; lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:rdptr_g|sub_parity4a0 ; 1 ;
; lp_rx:lp_rx|bcmpi_sync_n ; 1 ;
; Total number of inverted registers = 4 ; ;
+-----------------------------------------------------------------------------------------------+---------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+---------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+---------------------------------------------+----------------------------+
; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; |lp_rx_top_stratix|lp_rx:lp_rx|pos_edges[0] ; ;
+--------------------+-----------+---------------+----------------------+------------------------+---------------------------------------------+----------------------------+
+-----------------------------------------------------+
; Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo ;
+---------------------------------+-------+------+----+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+----+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+----+
+------------------------------------------------------------------------------+
; Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated ;
+---------------------------------+-------+------+-----------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+-----------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+-----------------------------+
+--------------------------------------------------------------------------------------------------------+
; Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:rdptr_g ;
+----------------+-------+------+------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH ; - ; sub_parity4a0 ;
; POWER_UP_LEVEL ; LOW ; - ; parity3 ;
+----------------+-------+------+------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:wrptr_g ;
+----------------+-------+------+------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH ; - ; sub_parity4a0 ;
; POWER_UP_LEVEL ; LOW ; - ; parity3 ;
+----------------+-------+------+------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------+
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -