📄 lp_rx_top_stratix.map.rpt
字号:
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2 processors ; 0.0% ;
+----------------------------+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------+
; ../../../source/verilog/lp_rx.v ; yes ; User Verilog HDL File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_rx.v ;
; lp_rx_top_stratix.v ; yes ; Auto-Found Verilog HDL File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v ;
; dcfifo.tdf ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/dcfifo.tdf ;
; lpm_counter.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_counter.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; altdpram.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altdpram.inc ;
; a_graycounter.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_graycounter.inc ;
; a_fefifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_fefifo.inc ;
; a_gray2bin.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_gray2bin.inc ;
; dffpipe.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/dffpipe.inc ;
; alt_sync_fifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/alt_sync_fifo.inc ;
; lpm_compare.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_compare.inc ;
; altsyncram_fifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altsyncram_fifo.inc ;
; aglobal111.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/aglobal111.inc ;
; db/dcfifo_0pm1.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/dcfifo_0pm1.tdf ;
; db/a_fefifo_qec.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/a_fefifo_qec.tdf ;
; db/a_fefifo_3bc.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/a_fefifo_3bc.tdf ;
; db/a_gray2bin_l5b.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/a_gray2bin_l5b.tdf ;
; db/a_graycounter_u16.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/a_graycounter_u16.tdf ;
; db/dpram_1541.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/dpram_1541.tdf ;
; db/altsyncram_grh1.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/altsyncram_grh1.tdf ;
; db/dffpipe_ed9.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/dffpipe_ed9.tdf ;
; db/alt_synch_pipe_mc8.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/alt_synch_pipe_mc8.tdf ;
; db/dffpipe_gd9.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/dffpipe_gd9.tdf ;
; db/add_sub_bvb.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/add_sub_bvb.tdf ;
; db/cntr_cua.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/cntr_cua.tdf ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 307 ;
; -- Combinational with no register ; 42 ;
; -- Register only ; 166 ;
; -- Combinational with a register ; 99 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 42 ;
; -- 3 input functions ; 59 ;
; -- 2 input functions ; 34 ;
; -- 1 input functions ; 6 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 269 ;
; -- arithmetic mode ; 38 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 9 ;
; -- asynchronous clear/load mode ; 231 ;
; ; ;
; Total registers ; 265 ;
; Total logic cells in carry chains ; 46 ;
; Virtual pins ; 37 ;
; I/O pins ; 10 ;
; Total memory bits ; 4224 ;
; Maximum fan-out node ; rst_n ;
; Maximum fan-out ; 231 ;
; Total fan-out ; 1813 ;
; Average fan-out ; 4.68 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
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