lp_rx_top_stratix.map.rpt

altera fpga 和ts201的linkport接口设计

Analysis & Synthesis report for lp_rx_top_stratix
Fri Apr 06 19:27:30 2012
Quartus II 32-bit Version 11.1 Build 173 11/01/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Registers Removed During Synthesis
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Multiplexer Restructuring Statistics (No Restructuring Performed)
 13. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo
 14. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated
 15. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:rdptr_g
 16. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|a_graycounter_u16:wrptr_g
 17. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dpram_1541:fiforam|altsyncram_grh1:altsyncram6
 18. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rdbuw
 19. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rdusedw
 20. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_rs_dbwp
 21. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp
 22. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp|dffpipe_gd9:dffpipe9
 23. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw
 24. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw
 25. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_ws_dgrp
 26. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|alt_synch_pipe_mc8:dffpipe_ws_dgrp|dffpipe_gd9:dffpipe9
 27. Source assignments for lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_0pm1:auto_generated|dffpipe_ed9:dffpipe_ws_nbrp
 28. Parameter Settings for User Entity Instance: Top-level Entity: |lp_rx_top_stratix
 29. Parameter Settings for User Entity Instance: lp_rx:lp_rx
 30. Parameter Settings for User Entity Instance: lp_rx:lp_rx|dcfifo:rx_fifo
 31. dcfifo Parameter Settings by Entity Instance
 32. Elapsed Time Per Partition
 33. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                            ;
+-----------------------------+-------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Apr 06 19:27:30 2012     ;
; Quartus II 32-bit Version   ; 11.1 Build 173 11/01/2011 SJ Full Version ;
; Revision Name               ; lp_rx_top_stratix                         ;
; Top-level Entity Name       ; lp_rx_top_stratix                         ;
; Family                      ; Stratix                                   ;
; Total logic elements        ; 307                                       ;
; Total pins                  ; 10                                        ;
; Total virtual pins          ; 37                                        ;
; Total memory bits           ; 4,224                                     ;
; DSP block 9-bit elements    ; 0                                         ;
; Total PLLs                  ; 0                                         ;
; Total DLLs                  ; 0                                         ;
+-----------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP1S10F484C5       ;                    ;
; Top-level entity name                                                      ; lp_rx_top_stratix  ; lp_rx_top_stratix  ;
; Family name                                                                ; Stratix            ; Stratix            ;
; VHDL Show LMF Mapping Messages                                             ; Off                ;                    ;
; Optimization Technique                                                     ; Speed              ; Balanced           ;
; Perform WYSIWYG Primitive Resynthesis                                      ; On                 ; Off                ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; Off                ; Off                ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;