rmulti.xco

无线通信FPGA设计-FPGA源码

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#
# Xilinx Core Generator version i+IP+122117
# Date: Sun Sep 09 15:50:11 2007
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vsx35
SET devicefamily = virtex4
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff668
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -12
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Multiplier family Xilinx,_Inc. 10.0
# END Select
# BEGIN Parameters
CSET ccmimp=Distributed_Memory
CSET clockenable=false
CSET component_name=rmulti
CSET constvalue=129
CSET dynamic_constant_reload=false
CSET multiplier_construction=Use_Mults
CSET multtype=Parallel_Multiplier
CSET optgoal=Speed
CSET outputwidthhigh=31
CSET outputwidthlow=0
CSET pipestages=4
CSET portatype=Signed
CSET portawidth=16
CSET portbtype=Signed
CSET portbwidth=16
CSET reloadable=false
CSET roundpoint=0
CSET sclrcepriority=SCLR_Overrides_CE
CSET syncclear=false
CSET use_custom_output_width=false
CSET use_load_done=false
CSET userounding=false
CSET zerodetect=false
# END Parameters
GENERATE
# CRC: cca2e784