3

秒脉冲

; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
; Analysis & Synthesis Message Level                           ; Medium             ; Medium             ;
+--------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                              ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                          ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------+
; ledwater.v                       ; yes             ; User Verilog HDL File  ; E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total logic elements                        ; 60      ;
;     -- Combinational with no register       ; 33      ;
;     -- Register only                        ; 12      ;
;     -- Combinational with a register        ; 15      ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 8       ;
;     -- 3 input functions                    ; 0       ;
;     -- 2 input functions                    ; 38      ;
;     -- 1 input functions                    ; 2       ;
;     -- 0 input functions                    ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 36      ;
;     -- arithmetic mode                      ; 24      ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 0       ;
;     -- asynchronous clear/load mode         ; 0       ;
;                                             ;         ;
; Total registers                             ; 27      ;
; Total logic cells in carry chains           ; 25      ;
; I/O pins                                    ; 2       ;
; Maximum fan-out node                        ; clk_50M ;
; Maximum fan-out                             ; 27      ;
; Total fan-out                               ; 150     ;
; Average fan-out                             ; 2.42    ;
+---------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |ledwater                  ; 60 (60)     ; 27           ; 0          ; 2    ; 0            ; 33 (33)      ; 12 (12)           ; 15 (15)          ; 25 (25)         ; 0 (0)      ; |ledwater           ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Sun Sep 11 14:48:05 2011
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater
Info: Found 1 design units, including 1 entities, in source file ledwater.v
    Info: Found entity 1: ledwater
Info: Elaborating entity "ledwater" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at ledwater.v(22): truncated value with size 32 to match size of target (25)
Info: Implemented 62 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 60 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 173 megabytes
    Info: Processing ended: Sun Sep 11 14:48:09 2011
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:02