3

秒脉冲

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_50M " "Info: Assuming node \"clk_50M\" is an undefined clock" {  } { { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 6 -1 0 } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_50M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50M register count\[4\] register count\[22\] 104.69 MHz 9.552 ns Internal " "Info: Clock \"clk_50M\" has Internal fmax of 104.69 MHz between source register \"count\[4\]\" and destination register \"count\[22\]\" (period= 9.552 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.843 ns + Longest register register " "Info: + Longest register to register delay is 8.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[4\] 1 REG LC_X5_Y2_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N0; Fanout = 4; REG Node = 'count\[4\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[4] } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.842 ns) + CELL(0.914 ns) 2.756 ns Equal0~1 2 COMB LC_X5_Y2_N2 1 " "Info: 2: + IC(1.842 ns) + CELL(0.914 ns) = 2.756 ns; Loc. = LC_X5_Y2_N2; Fanout = 1; COMB Node = 'Equal0~1'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.756 ns" { count[4] Equal0~1 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.730 ns) + CELL(0.511 ns) 4.997 ns Equal0~4 3 COMB LC_X5_Y1_N9 1 " "Info: 3: + IC(1.730 ns) + CELL(0.511 ns) = 4.997 ns; Loc. = LC_X5_Y1_N9; Fanout = 1; COMB Node = 'Equal0~4'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.241 ns" { Equal0~1 Equal0~4 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.200 ns) 5.929 ns Equal0~7 4 COMB LC_X5_Y1_N3 14 " "Info: 4: + IC(0.732 ns) + CELL(0.200 ns) = 5.929 ns; Loc. = LC_X5_Y1_N3; Fanout = 14; COMB Node = 'Equal0~7'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.932 ns" { Equal0~4 Equal0~7 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.323 ns) + CELL(0.591 ns) 8.843 ns count\[22\] 5 REG LC_X7_Y2_N9 4 " "Info: 5: + IC(2.323 ns) + CELL(0.591 ns) = 8.843 ns; Loc. = LC_X7_Y2_N9; Fanout = 4; REG Node = 'count\[22\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.914 ns" { Equal0~7 count[22] } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.216 ns ( 25.06 % ) " "Info: Total cell delay = 2.216 ns ( 25.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.627 ns ( 74.94 % ) " "Info: Total interconnect delay = 6.627 ns ( 74.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.843 ns" { count[4] Equal0~1 Equal0~4 Equal0~7 count[22] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "8.843 ns" { count[4] {} Equal0~1 {} Equal0~4 {} Equal0~7 {} count[22] {} } { 0.000ns 1.842ns 1.730ns 0.732ns 2.323ns } { 0.000ns 0.914ns 0.511ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50M destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50M\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50M 1 CLK PIN_12 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'clk_50M'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50M } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns count\[22\] 2 REG LC_X7_Y2_N9 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y2_N9; Fanout = 4; REG Node = 'count\[22\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_50M count[22] } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_50M count[22] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk_50M {} clk_50M~combout {} count[22] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50M source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk_50M\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50M 1 CLK PIN_12 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'clk_50M'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50M } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns count\[4\] 2 REG LC_X5_Y2_N0 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N0; Fanout = 4; REG Node = 'count\[4\]'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_50M count[4] } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_50M count[4] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk_50M {} clk_50M~combout {} count[4] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_50M count[22] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk_50M {} clk_50M~combout {} count[22] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_50M count[4] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk_50M {} clk_50M~combout {} count[4] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "8.843 ns" { count[4] Equal0~1 Equal0~4 Equal0~7 count[22] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "8.843 ns" { count[4] {} Equal0~1 {} Equal0~4 {} Equal0~7 {} count[22] {} } { 0.000ns 1.842ns 1.730ns 0.732ns 2.323ns } { 0.000ns 0.914ns 0.511ns 0.200ns 0.591ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_50M count[22] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk_50M {} clk_50M~combout {} count[22] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_50M count[4] } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk_50M {} clk_50M~combout {} count[4] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_50M led_out led_out~reg0 6.813 ns register " "Info: tco from clock \"clk_50M\" to destination pin \"led_out\" through register \"led_out~reg0\" is 6.813 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50M source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk_50M\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50M 1 CLK PIN_12 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'clk_50M'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50M } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns led_out~reg0 2 REG LC_X7_Y1_N4 1 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y1_N4; Fanout = 1; REG Node = 'led_out~reg0'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_50M led_out~reg0 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_50M led_out~reg0 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk_50M {} clk_50M~combout {} led_out~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.089 ns + Longest register pin " "Info: + Longest register to pin delay is 3.089 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_out~reg0 1 REG LC_X7_Y1_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N4; Fanout = 1; REG Node = 'led_out~reg0'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { led_out~reg0 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(2.322 ns) 3.089 ns led_out 2 PIN PIN_54 0 " "Info: 2: + IC(0.767 ns) + CELL(2.322 ns) = 3.089 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'led_out'" {  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.089 ns" { led_out~reg0 led_out } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/CPLD学习资料/Verilog参考例程/3、分频1秒/ledwater.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 75.17 % ) " "Info: Total cell delay = 2.322 ns ( 75.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.767 ns ( 24.83 % ) " "Info: Total interconnect delay = 0.767 ns ( 24.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.089 ns" { led_out~reg0 led_out } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.089 ns" { led_out~reg0 {} led_out {} } { 0.000ns 0.767ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_50M led_out~reg0 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk_50M {} clk_50M~combout {} led_out~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.089 ns" { led_out~reg0 led_out } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "3.089 ns" { led_out~reg0 {} led_out {} } { 0.000ns 0.767ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Peak virtual memory: 133 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 11 12:53:14 2011 " "Info: Processing ended: Sun Sep 11 12:53:14 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}