3

秒脉冲

; N/A                                     ; 133.87 MHz ( period = 7.470 ns )                    ; count[15] ; count[24] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.761 ns                ;
; N/A                                     ; 133.92 MHz ( period = 7.467 ns )                    ; count[18] ; count[24] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.758 ns                ;
; N/A                                     ; 133.94 MHz ( period = 7.466 ns )                    ; count[18] ; count[21] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.757 ns                ;
; N/A                                     ; 133.99 MHz ( period = 7.463 ns )                    ; count[7]  ; count[13] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.754 ns                ;
; N/A                                     ; 134.05 MHz ( period = 7.460 ns )                    ; count[11] ; count[16] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.751 ns                ;
; N/A                                     ; 134.25 MHz ( period = 7.449 ns )                    ; count[3]  ; div_clk   ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.740 ns                ;
; N/A                                     ; 134.34 MHz ( period = 7.444 ns )                    ; count[6]  ; count[20] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.735 ns                ;
; N/A                                     ; 134.35 MHz ( period = 7.443 ns )                    ; count[0]  ; count[19] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.734 ns                ;
; N/A                                     ; 134.39 MHz ( period = 7.441 ns )                    ; count[3]  ; count[20] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.732 ns                ;
; N/A                                     ; 134.43 MHz ( period = 7.439 ns )                    ; count[21] ; count[22] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.730 ns                ;
; N/A                                     ; 134.55 MHz ( period = 7.432 ns )                    ; count[9]  ; count[23] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.723 ns                ;
; N/A                                     ; 134.55 MHz ( period = 7.432 ns )                    ; count[13] ; count[23] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.723 ns                ;
; N/A                                     ; 134.59 MHz ( period = 7.430 ns )                    ; count[1]  ; count[19] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 134.63 MHz ( period = 7.428 ns )                    ; count[18] ; count[22] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.719 ns                ;
; N/A                                     ; 134.64 MHz ( period = 7.427 ns )                    ; count[8]  ; count[13] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.718 ns                ;
; N/A                                     ; 134.64 MHz ( period = 7.427 ns )                    ; count[10] ; count[13] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.718 ns                ;
; N/A                                     ; 134.77 MHz ( period = 7.420 ns )                    ; count[3]  ; count[17] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.711 ns                ;
; N/A                                     ; 134.81 MHz ( period = 7.418 ns )                    ; count[11] ; count[15] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.709 ns                ;
; N/A                                     ; 134.83 MHz ( period = 7.417 ns )                    ; count[7]  ; div_clk   ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.708 ns                ;
; N/A                                     ; 134.84 MHz ( period = 7.416 ns )                    ; count[5]  ; count[21] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.707 ns                ;
; N/A                                     ; 134.88 MHz ( period = 7.414 ns )                    ; count[12] ; count[15] ; clk_50M    ; clk_50M  ; None                        ; None                      ; 6.705 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.813 ns   ; led_out~reg0 ; led_out ; clk_50M    ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Sun Sep 11 14:48:41 2011
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ledwater -c ledwater
Info: Only one processor detected - disabling parallel compilation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_50M" is an undefined clock
Info: Clock "clk_50M" has Internal fmax of 104.69 MHz between source register "count[4]" and destination register "count[22]" (period= 9.552 ns)
    Info: + Longest register to register delay is 8.843 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N0; Fanout = 4; REG Node = 'count[4]'
        Info: 2: + IC(1.842 ns) + CELL(0.914 ns) = 2.756 ns; Loc. = LC_X5_Y2_N2; Fanout = 1; COMB Node = 'Equal0~1'
        Info: 3: + IC(1.730 ns) + CELL(0.511 ns) = 4.997 ns; Loc. = LC_X5_Y1_N9; Fanout = 1; COMB Node = 'Equal0~4'
        Info: 4: + IC(0.732 ns) + CELL(0.200 ns) = 5.929 ns; Loc. = LC_X5_Y1_N3; Fanout = 14; COMB Node = 'Equal0~7'
        Info: 5: + IC(2.323 ns) + CELL(0.591 ns) = 8.843 ns; Loc. = LC_X7_Y2_N9; Fanout = 4; REG Node = 'count[22]'
        Info: Total cell delay = 2.216 ns ( 25.06 % )
        Info: Total interconnect delay = 6.627 ns ( 74.94 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk_50M" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'clk_50M'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y2_N9; Fanout = 4; REG Node = 'count[22]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk_50M" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'clk_50M'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N0; Fanout = 4; REG Node = 'count[4]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk_50M" to destination pin "led_out" through register "led_out~reg0" is 6.813 ns
    Info: + Longest clock path from clock "clk_50M" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'clk_50M'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y1_N4; Fanout = 1; REG Node = 'led_out~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 3.089 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N4; Fanout = 1; REG Node = 'led_out~reg0'
        Info: 2: + IC(0.767 ns) + CELL(2.322 ns) = 3.089 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'led_out'
        Info: Total cell delay = 2.322 ns ( 75.17 % )
        Info: Total interconnect delay = 0.767 ns ( 24.83 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 133 megabytes
    Info: Processing ended: Sun Sep 11 14:48:46 2011
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:04