testctl.tan.qmsg

基于VHDL语言的频率计具有高速计频

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register div2clk register div2clk 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"div2clk\" and destination register \"div2clk\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div2clk 1 REG LC3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'div2clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "" { div2clk } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns div2clk 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'div2clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "8.000 ns" { div2clk div2clk } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 100.00 % " "Info: Total cell delay = 8.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "8.000 ns" { div2clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { div2clk div2clk } { 0.000ns 0.000ns } { 0.000ns 8.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 2; CLK Node = 'clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "" { clk } "NODE_NAME" } "" } } { "testctl.vhd" "" { Text "E:/日期/0517/fraq/testctl/testctl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns div2clk 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'div2clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "0.000 ns" { clk div2clk } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "3.000 ns" { clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out div2clk } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 2; CLK Node = 'clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "" { clk } "NODE_NAME" } "" } } { "testctl.vhd" "" { Text "E:/日期/0517/fraq/testctl/testctl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns div2clk 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'div2clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "0.000 ns" { clk div2clk } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "3.000 ns" { clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out div2clk } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "3.000 ns" { clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out div2clk } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "3.000 ns" { clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out div2clk } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "8.000 ns" { div2clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { div2clk div2clk } { 0.000ns 0.000ns } { 0.000ns 8.000ns } } } { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "3.000 ns" { clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out div2clk } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "3.000 ns" { clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out div2clk } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk load div2clk 17.000 ns register " "Info: tco from clock \"clk\" to destination pin \"load\" through register \"div2clk\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 2; CLK Node = 'clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "" { clk } "NODE_NAME" } "" } } { "testctl.vhd" "" { Text "E:/日期/0517/fraq/testctl/testctl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns div2clk 2 REG LC3 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'div2clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "0.000 ns" { clk div2clk } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "3.000 ns" { clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out div2clk } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div2clk 1 REG LC3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 4; REG Node = 'div2clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "" { div2clk } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns div2clk~13 2 COMB LC6 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC6; Fanout = 1; COMB Node = 'div2clk~13'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "9.000 ns" { div2clk div2clk~13 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns load 3 PIN PIN_10 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'load'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "4.000 ns" { div2clk~13 load } "NODE_NAME" } "" } } { "testctl.vhd" "" { Text "E:/日期/0517/fraq/testctl/testctl.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "13.000 ns" { div2clk div2clk~13 load } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { div2clk div2clk~13 load } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "3.000 ns" { clk div2clk } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out div2clk } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "13.000 ns" { div2clk div2clk~13 load } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { div2clk div2clk~13 load } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk clr_cnt 15.000 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"clr_cnt\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 2; CLK Node = 'clk'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "" { clk } "NODE_NAME" } "" } } { "testctl.vhd" "" { Text "E:/日期/0517/fraq/testctl/testctl.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns process1~2 2 COMB LC5 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'process1~2'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "8.000 ns" { clk process1~2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns clr_cnt 3 PIN PIN_11 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'clr_cnt'" {  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "4.000 ns" { process1~2 clr_cnt } "NODE_NAME" } "" } } { "testctl.vhd" "" { Text "E:/日期/0517/fraq/testctl/testctl.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 93.33 % " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.67 % " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" "" { Report "E:/日期/0517/fraq/testctl/db/testctl_cmp.qrpt" Compiler "testctl" "UNKNOWN" "V1" "E:/日期/0517/fraq/testctl/db/testctl.quartus_db" { Floorplan "E:/日期/0517/fraq/testctl/" "" "15.000 ns" { clk process1~2 clr_cnt } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.000 ns" { clk clk~out process1~2 clr_cnt } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 3.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 22 16:29:49 2006 " "Info: Processing ended: Mon May 22 16:29:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}