testctl.vhd

基于VHDL语言的频率计具有高速计频

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity testctl is
  port(clk:in std_logic;
      tsten: out std_logic;
      clr_cnt: out std_logic;
      load: out std_logic);
end entity testctl;
architecture bev of testctl is
   signal div2clk: std_logic;
   begin
   process(clk) is
   begin
    if clk'event and clk='1' then
    div2clk<=not div2clk;
    end if;
   end process;
   process(clk,div2clk) is
   begin
     if clk='0' and div2clk='0' then
     clr_cnt<='1';
     else clr_cnt<='0';
     end if;
   end process;
   load<=not div2clk;
   tsten<=div2clk;
 end architecture bev;