testctl.fit.eqn

基于VHDL语言的频率计具有高速计频

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--div2clk is div2clk at LC3
div2clk_reg_input = VCC;
div2clk = TFFE(div2clk_reg_input, GLOBAL(clk), , , );


--A1L6 is process1~2 at LC5
A1L6_p1_out = !div2clk & !clk;
A1L6_or_out = A1L6_p1_out;
A1L6 = A1L6_or_out;


--A1L4 is div2clk~13 at LC6
A1L4_or_out = !div2clk;
A1L4 = A1L4_or_out;


--clk is clk at PIN_83
--operation mode is input

clk = INPUT();


--tsten is tsten at PIN_12
--operation mode is output

tsten = OUTPUT(div2clk);


--clr_cnt is clr_cnt at PIN_11
--operation mode is output

clr_cnt = OUTPUT(A1L6);


--load is load at PIN_10
--operation mode is output

load = OUTPUT(A1L4);