fraq.tan.rpt

基于VHDL语言的频率计具有高速计频

; Device Name                                           ; EPM7128SLC84-15    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clkled          ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; clk             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; fsin            ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkled'                                                                                                                                                                              ;
+-------+----------------------------------+----------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                 ; To                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+----------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; dispscan:u11|sell[0] ; dispscan:u11|sell[2] ; clkled     ; clkled   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; dispscan:u11|sell[1] ; dispscan:u11|sell[2] ; clkled     ; clkled   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; dispscan:u11|sell[2] ; dispscan:u11|sell[2] ; clkled     ; clkled   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; dispscan:u11|sell[0] ; dispscan:u11|sell[1] ; clkled     ; clkled   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; dispscan:u11|sell[1] ; dispscan:u11|sell[1] ; clkled     ; clkled   ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; dispscan:u11|sell[0] ; dispscan:u11|sell[0] ; clkled     ; clkled   ; None                        ; None                      ; 8.000 ns                ;
+-------+----------------------------------+----------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                    ; To                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9]  ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[10] ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[11] ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[12] ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[13] ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[14] ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[15] ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[16] ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[17] ; oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;