📄 fraq.map.rpt
字号:
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+----------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: cnt10:u2|lpm_counter:cqi_rtl_7 ;
+------------------------+----------+---------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+----------+---------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+----------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: oscdiv:u0|lpm_counter:qn_rtl_8 ;
+------------------------+----------+---------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+----------+---------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 22 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+----------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/日期/0517/fraq/fraq.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Jun 07 16:44:03 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fraq -c fraq
Info: Found 14 design units, including 7 entities, in source file fraq.vhd
Info: Found design unit 1: cnt10-art
Info: Found design unit 2: reg32b-be
Info: Found design unit 3: oscdiv-fr
Info: Found design unit 4: testctl-bev
Info: Found design unit 5: dispscan-scan
Info: Found design unit 6: led-led
Info: Found design unit 7: fraq-beva
Info: Found entity 1: cnt10
Info: Found entity 2: reg32b
Info: Found entity 3: oscdiv
Info: Found entity 4: testctl
Info: Found entity 5: dispscan
Info: Found entity 6: led
Info: Found entity 7: fraq
Info: Elaborating entity "fraq" for the top level hierarchy
Info: Elaborating entity "oscdiv" for hierarchy "oscdiv:u0"
Info: Elaborating entity "testctl" for hierarchy "testctl:u1"
Info: Elaborating entity "cnt10" for hierarchy "cnt10:u2"
Info: Elaborating entity "reg32b" for hierarchy "reg32b:u10"
Info: Elaborating entity "dispscan" for hierarchy "dispscan:u11"
Warning: VHDL Process Statement warning at fraq.vhd(144): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(145): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(146): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(147): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(148): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(149): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(150): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(151): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(152): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(153): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(154): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(155): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(156): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(157): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(158): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(159): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(160): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(161): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(162): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(163): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(164): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(165): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(166): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(167): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(168): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(169): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(170): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(171): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(172): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(173): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(174): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at fraq.vhd(175): signal "d_in" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at fraq.vhd(176): OTHERS choice is never selected
Info: Elaborating entity "led" for hierarchy "led:u12"
Info: VHDL Case Statement information at fraq.vhd(219): OTHERS choice is never selected
Info: Inferred 9 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u9|cqi[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u8|cqi[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u7|cqi[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u6|cqi[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u5|cqi[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u4|cqi[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u3|cqi[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt10:u2|cqi[0]~8"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=22) from the following logic: "oscdiv:u0|qn[0]~0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "fsin" to global clock signal
Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Promoted clear signal driven by pin "resetled" to global clear signal
Info: Implemented 122 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 10 output pins
Info: Implemented 108 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings
Info: Processing ended: Wed Jun 07 16:44:13 2006
Info: Elapsed time: 00:00:10
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -