fraq.tan.qmsg

基于VHDL语言的频率计具有高速计频

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "30 " "Warning: Found 30 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[2\] " "Info: Detected ripple clock \"cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[2\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[1\] " "Info: Detected ripple clock \"cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[1\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[3\] " "Info: Detected ripple clock \"cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[0\] " "Info: Detected ripple clock \"cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u8\|lpm_counter:cqi_rtl_1\|dffs\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[2\] " "Info: Detected ripple clock \"cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[2\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[0\] " "Info: Detected ripple clock \"cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[3\] " "Info: Detected ripple clock \"cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[1\] " "Info: Detected ripple clock \"cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[1\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u7\|lpm_counter:cqi_rtl_2\|dffs\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[2\] " "Info: Detected ripple clock \"cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[2\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[0\] " "Info: Detected ripple clock \"cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[3\] " "Info: Detected ripple clock \"cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[1\] " "Info: Detected ripple clock \"cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[1\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u6\|lpm_counter:cqi_rtl_3\|dffs\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[2\] " "Info: Detected ripple clock \"cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[2\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[0\] " "Info: Detected ripple clock \"cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[3\] " "Info: Detected ripple clock \"cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[1\] " "Info: Detected ripple clock \"cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[1\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u5\|lpm_counter:cqi_rtl_4\|dffs\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[2\] " "Info: Detected ripple clock \"cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[2\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[0\] " "Info: Detected ripple clock \"cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[3\] " "Info: Detected ripple clock \"cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[1\] " "Info: Detected ripple clock \"cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[1\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u4\|lpm_counter:cqi_rtl_5\|dffs\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[2\] " "Info: Detected ripple clock \"cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[2\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[0\] " "Info: Detected ripple clock \"cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[3\] " "Info: Detected ripple clock \"cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[1\] " "Info: Detected ripple clock \"cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[1\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u3\|lpm_counter:cqi_rtl_6\|dffs\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[2\] " "Info: Detected ripple clock \"cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[2\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[0\] " "Info: Detected ripple clock \"cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[3\] " "Info: Detected ripple clock \"cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[1\] " "Info: Detected ripple clock \"cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[1\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt10:u2\|lpm_counter:cqi_rtl_7\|dffs\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "testctl:u1\|tsten " "Info: Detected ripple clock \"testctl:u1\|tsten\" as buffer" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 90 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "testctl:u1\|tsten" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[21\] " "Info: Detected ripple clock \"oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[21\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[21\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkled register dispscan:u11\|sell\[0\] register dispscan:u11\|sell\[2\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"clkled\" has Internal fmax of 76.92 MHz between source register \"dispscan:u11\|sell\[0\]\" and destination register \"dispscan:u11\|sell\[2\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dispscan:u11\|sell\[0\] 1 REG LC113 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC113; Fanout = 36; REG Node = 'dispscan:u11\|sell\[0\]'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "" { dispscan:u11|sell[0] } "NODE_NAME" } "" } } { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 126 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns dispscan:u11\|sell\[2\] 2 REG LC71 34 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC71; Fanout = 34; REG Node = 'dispscan:u11\|sell\[2\]'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "8.000 ns" { dispscan:u11|sell[0] dispscan:u11|sell[2] } "NODE_NAME" } "" } } { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 126 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "8.000 ns" { dispscan:u11|sell[0] dispscan:u11|sell[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { dispscan:u11|sell[0] dispscan:u11|sell[2] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkled destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clkled\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkled 1 CLK PIN_81 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 3; CLK Node = 'clkled'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "" { clkled } "NODE_NAME" } "" } } { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 237 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns dispscan:u11\|sell\[2\] 2 REG LC71 34 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC71; Fanout = 34; REG Node = 'dispscan:u11\|sell\[2\]'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "8.000 ns" { clkled dispscan:u11|sell[2] } "NODE_NAME" } "" } } { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 126 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "10.000 ns" { clkled dispscan:u11|sell[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clkled clkled~out dispscan:u11|sell[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkled source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"clkled\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clkled 1 CLK PIN_81 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 3; CLK Node = 'clkled'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "" { clkled } "NODE_NAME" } "" } } { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 237 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns dispscan:u11\|sell\[0\] 2 REG LC113 36 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC113; Fanout = 36; REG Node = 'dispscan:u11\|sell\[0\]'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "8.000 ns" { clkled dispscan:u11|sell[0] } "NODE_NAME" } "" } } { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 126 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "10.000 ns" { clkled dispscan:u11|sell[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clkled clkled~out dispscan:u11|sell[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "10.000 ns" { clkled dispscan:u11|sell[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clkled clkled~out dispscan:u11|sell[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "10.000 ns" { clkled dispscan:u11|sell[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clkled clkled~out dispscan:u11|sell[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 126 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 126 -1 0 } }  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "8.000 ns" { dispscan:u11|sell[0] dispscan:u11|sell[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { dispscan:u11|sell[0] dispscan:u11|sell[2] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "10.000 ns" { clkled dispscan:u11|sell[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clkled clkled~out dispscan:u11|sell[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "10.000 ns" { clkled dispscan:u11|sell[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { clkled clkled~out dispscan:u11|sell[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[9\] register oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[19\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[9\]\" and destination register \"oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[19\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[9\] 1 REG LC15 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC15; Fanout = 13; REG Node = 'oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[9\]'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "" { oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[19\] 2 REG LC3 3 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 3; REG Node = 'oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[19\]'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "8.000 ns" { oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "8.000 ns" { oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'clk'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "" { clk } "NODE_NAME" } "" } } { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 236 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[19\] 2 REG LC3 3 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 3; REG Node = 'oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[19\]'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "0.000 ns" { clk oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "3.000 ns" { clk oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 22 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 22; CLK Node = 'clk'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "" { clk } "NODE_NAME" } "" } } { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 236 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[9\] 2 REG LC15 13 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC15; Fanout = 13; REG Node = 'oscdiv:u0\|lpm_counter:qn_rtl_8\|dffs\[9\]'" {  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "0.000 ns" { clk oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "3.000 ns" { clk oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "3.000 ns" { clk oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "3.000 ns" { clk oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "8.000 ns" { oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "3.000 ns" { clk oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/日期/0517/fraq/db/fraq_cmp.qrpt" "" { Report "E:/日期/0517/fraq/db/fraq_cmp.qrpt" Compiler "fraq" "UNKNOWN" "V1" "E:/日期/0517/fraq/db/fraq.quartus_db" { Floorplan "E:/日期/0517/fraq/" "" "3.000 ns" { clk oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}