fraq.map.qmsg

基于VHDL语言的频率计具有高速计频

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(160) " "Warning: VHDL Process Statement warning at fraq.vhd(160): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 160 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(161) " "Warning: VHDL Process Statement warning at fraq.vhd(161): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 161 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(162) " "Warning: VHDL Process Statement warning at fraq.vhd(162): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 162 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(163) " "Warning: VHDL Process Statement warning at fraq.vhd(163): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 163 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(164) " "Warning: VHDL Process Statement warning at fraq.vhd(164): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 164 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(165) " "Warning: VHDL Process Statement warning at fraq.vhd(165): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 165 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(166) " "Warning: VHDL Process Statement warning at fraq.vhd(166): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 166 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(167) " "Warning: VHDL Process Statement warning at fraq.vhd(167): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 167 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(168) " "Warning: VHDL Process Statement warning at fraq.vhd(168): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 168 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(169) " "Warning: VHDL Process Statement warning at fraq.vhd(169): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 169 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(170) " "Warning: VHDL Process Statement warning at fraq.vhd(170): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 170 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(171) " "Warning: VHDL Process Statement warning at fraq.vhd(171): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 171 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(172) " "Warning: VHDL Process Statement warning at fraq.vhd(172): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 172 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(173) " "Warning: VHDL Process Statement warning at fraq.vhd(173): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 173 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(174) " "Warning: VHDL Process Statement warning at fraq.vhd(174): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 174 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(175) " "Warning: VHDL Process Statement warning at fraq.vhd(175): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 175 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "fraq.vhd(176) " "Info: VHDL Case Statement information at fraq.vhd(176): OTHERS choice is never selected" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 176 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:u12 " "Info: Elaborating entity \"led\" for hierarchy \"led:u12\"" {  } { { "fraq.vhd" "u12" { Text "E:/日期/0517/fraq/fraq.vhd" 315 -1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "fraq.vhd(219) " "Info: VHDL Case Statement information at fraq.vhd(219): OTHERS choice is never selected" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 219 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "9 " "Info: Inferred 9 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u9\|cqi\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u9\|cqi\[0\]~8\"" {  } { { "fraq.vhd" "cqi\[0\]~8" { Text "E:/日期/0517/fraq/fraq.vhd" 15 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u8\|cqi\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u8\|cqi\[0\]~8\"" {  } { { "fraq.vhd" "cqi\[0\]~8" { Text "E:/日期/0517/fraq/fraq.vhd" 15 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u7\|cqi\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u7\|cqi\[0\]~8\"" {  } { { "fraq.vhd" "cqi\[0\]~8" { Text "E:/日期/0517/fraq/fraq.vhd" 15 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u6\|cqi\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u6\|cqi\[0\]~8\"" {  } { { "fraq.vhd" "cqi\[0\]~8" { Text "E:/日期/0517/fraq/fraq.vhd" 15 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u5\|cqi\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u5\|cqi\[0\]~8\"" {  } { { "fraq.vhd" "cqi\[0\]~8" { Text "E:/日期/0517/fraq/fraq.vhd" 15 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u4\|cqi\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u4\|cqi\[0\]~8\"" {  } { { "fraq.vhd" "cqi\[0\]~8" { Text "E:/日期/0517/fraq/fraq.vhd" 15 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u3\|cqi\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u3\|cqi\[0\]~8\"" {  } { { "fraq.vhd" "cqi\[0\]~8" { Text "E:/日期/0517/fraq/fraq.vhd" 15 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt10:u2\|cqi\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt10:u2\|cqi\[0\]~8\"" {  } { { "fraq.vhd" "cqi\[0\]~8" { Text "E:/日期/0517/fraq/fraq.vhd" 15 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "oscdiv:u0\|qn\[0\]~0 22 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=22) from the following logic: \"oscdiv:u0\|qn\[0\]~0\"" {  } { { "fraq.vhd" "qn\[0\]~0" { Text "E:/日期/0517/fraq/fraq.vhd" 70 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "fsin " "Info: Promoted clock signal driven by pin \"fsin\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "resetled " "Info: Promoted clear signal driven by pin \"resetled\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "122 " "Info: Implemented 122 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "108 " "Info: Implemented 108 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 07 16:44:13 2006 " "Info: Processing ended: Wed Jun 07 16:44:13 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}