fraq.map.qmsg

基于VHDL语言的频率计具有高速计频

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 07 16:44:03 2006 " "Info: Processing started: Wed Jun 07 16:44:03 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fraq -c fraq " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fraq -c fraq" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fraq.vhd 14 7 " "Info: Found 14 design units, including 7 entities, in source file fraq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt10-art " "Info: Found design unit 1: cnt10-art" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 reg32b-be " "Info: Found design unit 2: reg32b-be" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 48 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 oscdiv-fr " "Info: Found design unit 3: oscdiv-fr" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 68 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 testctl-bev " "Info: Found design unit 4: testctl-bev" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 94 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 dispscan-scan " "Info: Found design unit 5: dispscan-scan" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 125 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 led-led " "Info: Found design unit 6: led-led" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 196 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 fraq-beva " "Info: Found design unit 7: fraq-beva" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 250 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt10 " "Info: Found entity 1: cnt10" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 4 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 reg32b " "Info: Found entity 2: reg32b" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 43 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 oscdiv " "Info: Found entity 3: oscdiv" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 testctl " "Info: Found entity 4: testctl" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 88 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 dispscan " "Info: Found entity 5: dispscan" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 118 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 led " "Info: Found entity 6: led" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 185 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 fraq " "Info: Found entity 7: fraq" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 234 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fraq " "Info: Elaborating entity \"fraq\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "oscdiv oscdiv:u0 " "Info: Elaborating entity \"oscdiv\" for hierarchy \"oscdiv:u0\"" {  } { { "fraq.vhd" "u0" { Text "E:/日期/0517/fraq/fraq.vhd" 302 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "testctl testctl:u1 " "Info: Elaborating entity \"testctl\" for hierarchy \"testctl:u1\"" {  } { { "fraq.vhd" "u1" { Text "E:/日期/0517/fraq/fraq.vhd" 303 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt10 cnt10:u2 " "Info: Elaborating entity \"cnt10\" for hierarchy \"cnt10:u2\"" {  } { { "fraq.vhd" "u2" { Text "E:/日期/0517/fraq/fraq.vhd" 304 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg32b reg32b:u10 " "Info: Elaborating entity \"reg32b\" for hierarchy \"reg32b:u10\"" {  } { { "fraq.vhd" "u10" { Text "E:/日期/0517/fraq/fraq.vhd" 312 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dispscan dispscan:u11 " "Info: Elaborating entity \"dispscan\" for hierarchy \"dispscan:u11\"" {  } { { "fraq.vhd" "u11" { Text "E:/日期/0517/fraq/fraq.vhd" 313 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(144) " "Warning: VHDL Process Statement warning at fraq.vhd(144): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 144 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(145) " "Warning: VHDL Process Statement warning at fraq.vhd(145): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 145 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(146) " "Warning: VHDL Process Statement warning at fraq.vhd(146): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 146 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(147) " "Warning: VHDL Process Statement warning at fraq.vhd(147): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 147 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(148) " "Warning: VHDL Process Statement warning at fraq.vhd(148): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 148 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(149) " "Warning: VHDL Process Statement warning at fraq.vhd(149): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 149 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(150) " "Warning: VHDL Process Statement warning at fraq.vhd(150): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 150 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(151) " "Warning: VHDL Process Statement warning at fraq.vhd(151): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 151 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(152) " "Warning: VHDL Process Statement warning at fraq.vhd(152): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 152 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(153) " "Warning: VHDL Process Statement warning at fraq.vhd(153): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 153 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(154) " "Warning: VHDL Process Statement warning at fraq.vhd(154): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 154 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(155) " "Warning: VHDL Process Statement warning at fraq.vhd(155): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 155 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(156) " "Warning: VHDL Process Statement warning at fraq.vhd(156): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 156 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(157) " "Warning: VHDL Process Statement warning at fraq.vhd(157): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 157 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(158) " "Warning: VHDL Process Statement warning at fraq.vhd(158): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 158 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d_in fraq.vhd(159) " "Warning: VHDL Process Statement warning at fraq.vhd(159): signal \"d_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fraq.vhd" "" { Text "E:/日期/0517/fraq/fraq.vhd" 159 0 0 } }  } 0}