fraq.tan.summary

基于VHDL语言的频率计具有高速计频

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 45.000 ns
From           : reg32b:u10|dout[29]
To             : led_f
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 15.000 ns
From           : resetled
To             : selled[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'fsin'
Slack          : N/A
Required Time  : None
Actual Time    : 76.92 MHz ( period = 13.000 ns )
From           : cnt10:u2|lpm_counter:cqi_rtl_7|dffs[0]
To             : cnt10:u2|lpm_counter:cqi_rtl_7|dffs[1]
From Clock     : fsin
To Clock       : fsin
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 76.92 MHz ( period = 13.000 ns )
From           : oscdiv:u0|lpm_counter:qn_rtl_8|dffs[9]
To             : oscdiv:u0|lpm_counter:qn_rtl_8|dffs[19]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clkled'
Slack          : N/A
Required Time  : None
Actual Time    : 76.92 MHz ( period = 13.000 ns )
From           : dispscan:u11|sell[0]
To             : dispscan:u11|sell[0]
From Clock     : clkled
To Clock       : clkled
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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