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📄 cnt10.map.eqn

📁 基于VHDL语言的频率计具有高速计频
💻 EQN
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_dffs[1] is lpm_counter:cqi_rtl_0|dffs[1]
B1_dffs[1]_p1_out = !B1_dffs[3] & B1_dffs[0] & !B1_dffs[1];
B1_dffs[1]_p4_out = !B1_dffs[3] & !B1_dffs[0] & B1_dffs[1];
B1_dffs[1]_or_out = B1_dffs[1]_p1_out # B1_dffs[1]_p4_out;
B1_dffs[1]_reg_input = B1_dffs[1]_or_out;
B1_dffs[1] = DFFE(B1_dffs[1]_reg_input, GLOBAL(clk), !clr, , ena);


--B1_dffs[2] is lpm_counter:cqi_rtl_0|dffs[2]
B1_dffs[2]_p1_out = !B1_dffs[3] & B1_dffs[0] & B1_dffs[1];
B1_dffs[2]_p4_out = B1_dffs[3] & B1_dffs[2];
B1_dffs[2]_or_out = B1_dffs[2]_p1_out # B1_dffs[2]_p4_out;
B1_dffs[2]_reg_input = B1_dffs[2]_or_out;
B1_dffs[2] = TFFE(B1_dffs[2]_reg_input, GLOBAL(clk), !clr, , ena);


--B1_dffs[3] is lpm_counter:cqi_rtl_0|dffs[3]
B1_dffs[3]_p1_out = B1_dffs[0] & B1_dffs[1] & B1_dffs[2] & !B1_dffs[3];
B1_dffs[3]_p4_out = !B1_dffs[0] & !B1_dffs[1] & !B1_dffs[2] & B1_dffs[3];
B1_dffs[3]_or_out = B1_dffs[3]_p1_out # B1_dffs[3]_p4_out;
B1_dffs[3]_reg_input = B1_dffs[3]_or_out;
B1_dffs[3] = DFFE(B1_dffs[3]_reg_input, GLOBAL(clk), !clr, , ena);


--B1_dffs[0] is lpm_counter:cqi_rtl_0|dffs[0]
B1_dffs[0]_p1_out = !B1_dffs[0] & !B1_dffs[3];
B1_dffs[0]_p4_out = !B1_dffs[0] & !B1_dffs[1] & !B1_dffs[2];
B1_dffs[0]_or_out = B1_dffs[0]_p1_out # B1_dffs[0]_p4_out;
B1_dffs[0]_reg_input = B1_dffs[0]_or_out;
B1_dffs[0] = DFFE(B1_dffs[0]_reg_input, GLOBAL(clk), !clr, , ena);


--A1L01 is reduce_nor~1
A1L01_p1_out = B1_dffs[0] & B1_dffs[3] & !B1_dffs[1] & !B1_dffs[2];
A1L01_or_out = A1L01_p1_out;
A1L01 = A1L01_or_out;


--clk is clk
--operation mode is input

clk = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--ena is ena
--operation mode is input

ena = INPUT();


--cq[1] is cq[1]
--operation mode is output

cq[1] = OUTPUT(B1_dffs[1]);


--cq[2] is cq[2]
--operation mode is output

cq[2] = OUTPUT(B1_dffs[2]);


--cq[3] is cq[3]
--operation mode is output

cq[3] = OUTPUT(B1_dffs[3]);


--cq[0] is cq[0]
--operation mode is output

cq[0] = OUTPUT(B1_dffs[0]);


--carry_out is carry_out
--operation mode is output

carry_out = OUTPUT(A1L01);


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