📄 cnt10.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
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-- applicable agreement for further details.
--B1_dffs[1] is lpm_counter:cqi_rtl_0|dffs[1] at LC11
B1_dffs[1]_p1_out = !B1_dffs[3] & B1_dffs[0] & !B1_dffs[1];
B1_dffs[1]_p4_out = !B1_dffs[3] & !B1_dffs[0] & B1_dffs[1];
B1_dffs[1]_or_out = B1_dffs[1]_p1_out # B1_dffs[1]_p4_out;
B1_dffs[1]_reg_input = B1_dffs[1]_or_out;
B1_dffs[1] = DFFE(B1_dffs[1]_reg_input, GLOBAL(clk), !clr, , ena);
--B1_dffs[2] is lpm_counter:cqi_rtl_0|dffs[2] at LC8
B1_dffs[2]_p1_out = !B1_dffs[3] & B1_dffs[0] & B1_dffs[1];
B1_dffs[2]_p4_out = B1_dffs[3] & B1_dffs[2];
B1_dffs[2]_or_out = B1_dffs[2]_p1_out # B1_dffs[2]_p4_out;
B1_dffs[2]_reg_input = B1_dffs[2]_or_out;
B1_dffs[2] = TFFE(B1_dffs[2]_reg_input, GLOBAL(clk), !clr, , ena);
--B1_dffs[3] is lpm_counter:cqi_rtl_0|dffs[3] at LC6
B1_dffs[3]_p1_out = B1_dffs[0] & B1_dffs[1] & B1_dffs[2] & !B1_dffs[3];
B1_dffs[3]_p4_out = !B1_dffs[0] & !B1_dffs[1] & !B1_dffs[2] & B1_dffs[3];
B1_dffs[3]_or_out = B1_dffs[3]_p1_out # B1_dffs[3]_p4_out;
B1_dffs[3]_reg_input = B1_dffs[3]_or_out;
B1_dffs[3] = DFFE(B1_dffs[3]_reg_input, GLOBAL(clk), !clr, , ena);
--B1_dffs[0] is lpm_counter:cqi_rtl_0|dffs[0] at LC5
B1_dffs[0]_p1_out = !B1_dffs[0] & !B1_dffs[3];
B1_dffs[0]_p4_out = !B1_dffs[0] & !B1_dffs[1] & !B1_dffs[2];
B1_dffs[0]_or_out = B1_dffs[0]_p1_out # B1_dffs[0]_p4_out;
B1_dffs[0]_reg_input = B1_dffs[0]_or_out;
B1_dffs[0] = DFFE(B1_dffs[0]_reg_input, GLOBAL(clk), !clr, , ena);
--A1L01 is reduce_nor~1 at LC3
A1L01_p1_out = B1_dffs[0] & B1_dffs[3] & !B1_dffs[1] & !B1_dffs[2];
A1L01_or_out = A1L01_p1_out;
A1L01 = A1L01_or_out;
--clk is clk at PIN_83
--operation mode is input
clk = INPUT();
--clr is clr at PIN_81
--operation mode is input
clr = INPUT();
--ena is ena at PIN_52
--operation mode is input
ena = INPUT();
--cq[1] is cq[1] at PIN_8
--operation mode is output
cq[1] = OUTPUT(B1_dffs[1]);
--cq[2] is cq[2] at PIN_9
--operation mode is output
cq[2] = OUTPUT(B1_dffs[2]);
--cq[3] is cq[3] at PIN_10
--operation mode is output
cq[3] = OUTPUT(B1_dffs[3]);
--cq[0] is cq[0] at PIN_11
--operation mode is output
cq[0] = OUTPUT(B1_dffs[0]);
--carry_out is carry_out at PIN_12
--operation mode is output
carry_out = OUTPUT(A1L01);
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