📄 reg32b.tan.qmsg
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{ "Info" "ITAN_NO_REG2REG_EXIST" "load " "Info: No valid register-to-register data paths exist for clock \"load\"" { } { } 0}
{ "Info" "ITDB_TSU_RESULT" "dout\[15\]~reg0 din\[15\] load 11.000 ns register " "Info: tsu for register \"dout\[15\]~reg0\" (data pin = \"din\[15\]\", clock pin = \"load\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns din\[15\] 1 PIN PIN_50 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_50; Fanout = 1; PIN Node = 'din\[15\]'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "" { din[15] } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns dout\[15\]~reg0 2 REG LC35 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 1; REG Node = 'dout\[15\]~reg0'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "8.000 ns" { din[15] dout[15]~reg0 } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "10.000 ns" { din[15] dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { din[15] din[15]~out dout[15]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "load destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"load\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns load 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'load'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "" { load } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns dout\[15\]~reg0 2 REG LC35 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC35; Fanout = 1; REG Node = 'dout\[15\]~reg0'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "0.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "3.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { load load~out dout[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "10.000 ns" { din[15] dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { din[15] din[15]~out dout[15]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "3.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { load load~out dout[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "load dout\[15\] dout\[15\]~reg0 8.000 ns register " "Info: tco from clock \"load\" to destination pin \"dout\[15\]\" through register \"dout\[15\]~reg0\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "load source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"load\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns load 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'load'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "" { load } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns dout\[15\]~reg0 2 REG LC35 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC35; Fanout = 1; REG Node = 'dout\[15\]~reg0'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "0.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "3.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { load load~out dout[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[15\]~reg0 1 REG LC35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 1; REG Node = 'dout\[15\]~reg0'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "" { dout[15]~reg0 } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns dout\[15\] 2 PIN PIN_31 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'dout\[15\]'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "4.000 ns" { dout[15]~reg0 dout[15] } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "4.000 ns" { dout[15]~reg0 dout[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { dout[15]~reg0 dout[15] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } } } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "3.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { load load~out dout[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "4.000 ns" { dout[15]~reg0 dout[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { dout[15]~reg0 dout[15] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "dout\[15\]~reg0 din\[15\] load -3.000 ns register " "Info: th for register \"dout\[15\]~reg0\" (data pin = \"din\[15\]\", clock pin = \"load\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "load destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"load\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns load 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'load'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "" { load } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns dout\[15\]~reg0 2 REG LC35 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC35; Fanout = 1; REG Node = 'dout\[15\]~reg0'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "0.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "3.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { load load~out dout[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns din\[15\] 1 PIN PIN_50 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_50; Fanout = 1; PIN Node = 'din\[15\]'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "" { din[15] } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns dout\[15\]~reg0 2 REG LC35 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 1; REG Node = 'dout\[15\]~reg0'" { } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "8.000 ns" { din[15] dout[15]~reg0 } "NODE_NAME" } "" } } { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" { } { } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "10.000 ns" { din[15] dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { din[15] din[15]~out dout[15]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } } 0} } { { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "3.000 ns" { load dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { load load~out dout[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" "" { Report "E:/日期/0517/fraq/reg32b/db/reg32b_cmp.qrpt" Compiler "reg32b" "UNKNOWN" "V1" "E:/日期/0517/fraq/reg32b/db/reg32b.quartus_db" { Floorplan "E:/日期/0517/fraq/reg32b/" "" "10.000 ns" { din[15] dout[15]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { din[15] din[15]~out dout[15]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 22 16:11:35 2006 " "Info: Processing ended: Mon May 22 16:11:35 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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