reg32b.map.qmsg

基于VHDL语言的频率计具有高速计频

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 22 16:11:28 2006 " "Info: Processing started: Mon May 22 16:11:28 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off reg32b -c reg32b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off reg32b -c reg32b" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg32b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg32b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg32b-be " "Info: Found design unit 1: reg32b-be" {  } { { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg32b " "Info: Found entity 1: reg32b" {  } { { "reg32b.vhd" "" { Text "E:/日期/0517/fraq/reg32b/reg32b.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "reg32b " "Info: Elaborating entity \"reg32b\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "load " "Info: Promoted clock signal driven by pin \"load\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "49 " "Info: Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "16 " "Info: Implemented 16 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 22 16:11:29 2006 " "Info: Processing ended: Mon May 22 16:11:29 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}