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📄 reg32b.fit.eqn

📁 基于VHDL语言的频率计具有高速计频
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L84Q is dout[14]~reg0 at LC17
A1L84Q_or_out = din[14];
A1L84Q_reg_input = A1L84Q_or_out;
A1L84Q = DFFE(A1L84Q_reg_input, GLOBAL(load), , , );


--A1L64Q is dout[13]~reg0 at LC19
A1L64Q_or_out = din[13];
A1L64Q_reg_input = A1L64Q_or_out;
A1L64Q = DFFE(A1L64Q_reg_input, GLOBAL(load), , , );


--A1L44Q is dout[12]~reg0 at LC21
A1L44Q_or_out = din[12];
A1L44Q_reg_input = A1L44Q_or_out;
A1L44Q = DFFE(A1L44Q_reg_input, GLOBAL(load), , , );


--A1L24Q is dout[11]~reg0 at LC24
A1L24Q_or_out = din[11];
A1L24Q_reg_input = A1L24Q_or_out;
A1L24Q = DFFE(A1L24Q_reg_input, GLOBAL(load), , , );


--A1L04Q is dout[10]~reg0 at LC25
A1L04Q_or_out = din[10];
A1L04Q_reg_input = A1L04Q_or_out;
A1L04Q = DFFE(A1L04Q_reg_input, GLOBAL(load), , , );


--A1L83Q is dout[9]~reg0 at LC27
A1L83Q_or_out = din[9];
A1L83Q_reg_input = A1L83Q_or_out;
A1L83Q = DFFE(A1L83Q_reg_input, GLOBAL(load), , , );


--A1L63Q is dout[8]~reg0 at LC29
A1L63Q_or_out = din[8];
A1L63Q_reg_input = A1L63Q_or_out;
A1L63Q = DFFE(A1L63Q_reg_input, GLOBAL(load), , , );


--A1L43Q is dout[7]~reg0 at LC16
A1L43Q_or_out = din[7];
A1L43Q_reg_input = A1L43Q_or_out;
A1L43Q = DFFE(A1L43Q_reg_input, GLOBAL(load), , , );


--A1L23Q is dout[6]~reg0 at LC14
A1L23Q_or_out = din[6];
A1L23Q_reg_input = A1L23Q_or_out;
A1L23Q = DFFE(A1L23Q_reg_input, GLOBAL(load), , , );


--A1L03Q is dout[5]~reg0 at LC13
A1L03Q_or_out = din[5];
A1L03Q_reg_input = A1L03Q_or_out;
A1L03Q = DFFE(A1L03Q_reg_input, GLOBAL(load), , , );


--A1L82Q is dout[4]~reg0 at LC11
A1L82Q_or_out = din[4];
A1L82Q_reg_input = A1L82Q_or_out;
A1L82Q = DFFE(A1L82Q_reg_input, GLOBAL(load), , , );


--A1L62Q is dout[3]~reg0 at LC8
A1L62Q_or_out = din[3];
A1L62Q_reg_input = A1L62Q_or_out;
A1L62Q = DFFE(A1L62Q_reg_input, GLOBAL(load), , , );


--A1L42Q is dout[2]~reg0 at LC6
A1L42Q_or_out = din[2];
A1L42Q_reg_input = A1L42Q_or_out;
A1L42Q = DFFE(A1L42Q_reg_input, GLOBAL(load), , , );


--A1L22Q is dout[1]~reg0 at LC5
A1L22Q_or_out = din[1];
A1L22Q_reg_input = A1L22Q_or_out;
A1L22Q = DFFE(A1L22Q_reg_input, GLOBAL(load), , , );


--A1L02Q is dout[0]~reg0 at LC3
A1L02Q_or_out = din[0];
A1L02Q_reg_input = A1L02Q_or_out;
A1L02Q = DFFE(A1L02Q_reg_input, GLOBAL(load), , , );


--A1L05Q is dout[15]~reg0 at LC35
A1L05Q_or_out = din[15];
A1L05Q_reg_input = A1L05Q_or_out;
A1L05Q = DFFE(A1L05Q_reg_input, GLOBAL(load), , , );


--load is load at PIN_83
--operation mode is input

load = INPUT();


--din[0] is din[0] at PIN_33
--operation mode is input

din[0] = INPUT();


--din[1] is din[1] at PIN_61
--operation mode is input

din[1] = INPUT();


--din[2] is din[2] at PIN_81
--operation mode is input

din[2] = INPUT();


--din[3] is din[3] at PIN_52
--operation mode is input

din[3] = INPUT();


--din[4] is din[4] at PIN_24
--operation mode is input

din[4] = INPUT();


--din[5] is din[5] at PIN_80
--operation mode is input

din[5] = INPUT();


--din[6] is din[6] at PIN_60
--operation mode is input

din[6] = INPUT();


--din[7] is din[7] at PIN_51
--operation mode is input

din[7] = INPUT();


--din[8] is din[8] at PIN_34
--operation mode is input

din[8] = INPUT();


--din[9] is din[9] at PIN_70
--operation mode is input

din[9] = INPUT();


--din[10] is din[10] at PIN_25
--operation mode is input

din[10] = INPUT();


--din[11] is din[11] at PIN_79
--operation mode is input

din[11] = INPUT();


--din[12] is din[12] at PIN_77
--operation mode is input

din[12] = INPUT();


--din[13] is din[13] at PIN_58
--operation mode is input

din[13] = INPUT();


--din[14] is din[14] at PIN_35
--operation mode is input

din[14] = INPUT();


--din[15] is din[15] at PIN_50
--operation mode is input

din[15] = INPUT();


--dout[0] is dout[0] at PIN_12
--operation mode is output

dout[0] = OUTPUT(A1L02Q);


--dout[1] is dout[1] at PIN_11
--operation mode is output

dout[1] = OUTPUT(A1L22Q);


--dout[2] is dout[2] at PIN_10
--operation mode is output

dout[2] = OUTPUT(A1L42Q);


--dout[3] is dout[3] at PIN_9
--operation mode is output

dout[3] = OUTPUT(A1L62Q);


--dout[4] is dout[4] at PIN_8
--operation mode is output

dout[4] = OUTPUT(A1L82Q);


--dout[5] is dout[5] at PIN_6
--operation mode is output

dout[5] = OUTPUT(A1L03Q);


--dout[6] is dout[6] at PIN_5
--operation mode is output

dout[6] = OUTPUT(A1L23Q);


--dout[7] is dout[7] at PIN_4
--operation mode is output

dout[7] = OUTPUT(A1L43Q);


--dout[8] is dout[8] at PIN_15
--operation mode is output

dout[8] = OUTPUT(A1L63Q);


--dout[9] is dout[9] at PIN_16
--operation mode is output

dout[9] = OUTPUT(A1L83Q);


--dout[10] is dout[10] at PIN_17
--operation mode is output

dout[10] = OUTPUT(A1L04Q);


--dout[11] is dout[11] at PIN_18
--operation mode is output

dout[11] = OUTPUT(A1L24Q);


--dout[12] is dout[12] at PIN_20
--operation mode is output

dout[12] = OUTPUT(A1L44Q);


--dout[13] is dout[13] at PIN_21
--operation mode is output

dout[13] = OUTPUT(A1L64Q);


--dout[14] is dout[14] at PIN_22
--operation mode is output

dout[14] = OUTPUT(A1L84Q);


--dout[15] is dout[15] at PIN_31
--operation mode is output

dout[15] = OUTPUT(A1L05Q);






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