four_mult_two_add_inst.v

来自「FIR FILTER verilog code」· Verilog 代码 · 共 15 行

four_mult_two_add	four_mult_two_add_inst (
	.aclr0 ( aclr0_sig ),
	.clock0 ( clock0_sig ),
	.dataa_0 ( dataa_0_sig ),
	.dataa_1 ( dataa_1_sig ),
	.datab_0 ( datab_0_sig ),
	.dataa_2 ( dataa_2_sig ),
	.datab_1 ( datab_1_sig ),
	.ena0 ( ena0_sig ),
	.dataa_3 ( dataa_3_sig ),
	.datab_2 ( datab_2_sig ),
	.datab_3 ( datab_3_sig ),
	.result ( result_sig )
	);