hex2led_common_anode.v

使用FPGA控制数码管,在数码管上动态的显示数字,很使用,可以直接作为其他模块的子模块,直接调用

////////////////////////////////////////////////////////////////////////////////
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// *  RICHIC CONFIDENTIAL PROPRIETARY NOTE                                     *
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// *  This software contains information confidential and proprietary to       *
// *  RicHic Inc.It shall not be reproduced in whole or in part or transferred *
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// *  written consent of RicHic Inc.                                           *
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// *                All rights reserved                                        * 
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//
// (C) 2004 [e-mail];     
//     http://www.richic.com
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////////////////////////////////////////////////////////////////////////////////

module hex2led_common_anode (hex, led) ;

input [3:0] hex ;
output [6:0] led ;

reg [6:0] led;

//hex-to-seven-segment decoder
//
// segment encoding
//      0
//     ---  
//  5 |   | 1
//     ---   <- 6
//  4 |   | 2
//     ---
//      3

always @(hex)
begin
    case (hex)
	4'b0001 : led = 7'b1111001;	//1
	4'b0010 : led = 7'b0100100;	//2
	4'b0011 : led = 7'b0110000;	//3
	4'b0100 : led = 7'b0011001;	//4
	4'b0101 : led = 7'b0010010;	//5
	4'b0110 : led = 7'b0000010;	//6
	4'b0111 : led = 7'b1111000;	//7
	4'b1000 : led = 7'b0000000;	//8
	4'b1001 : led = 7'b0010000;	//9
	4'b1010 : led = 7'b0001000;	//A
	4'b1011 : led = 7'b0000011;	//b
	4'b1100 : led = 7'b1000110;	//C
	4'b1101 : led = 7'b0100001;	//d
	4'b1110 : led = 7'b0000110;	//E
	4'b1111 : led = 7'b0001110;	//F
	default : led = 7'b1000000;	//0
    endcase
end

endmodule