led_top1.v

来自「使用FPGA控制数码管,在数码管上动态的显示数字,很使用,可以直接作为其他模块的」· Verilog 代码 · 共 32 行

////////////////////////////////////////////////////////////////////////////////
// *****************************************************************************
// *  RICHIC CONFIDENTIAL PROPRIETARY NOTE                                     *
// *                                                                           *
// *  This software contains information confidential and proprietary to       *
// *  RicHic Inc.It shall not be reproduced in whole or in part or transferred *
// *  to other documents, or disclosed to third parties, or used for any       *
// *  purpose other than that for which it was obtained, without the prior     *
// *  written consent of RicHic Inc.                                           *
// *             (c) 2003, 2004, 2005 RicHic Inc.                              *
// *                All rights reserved                                        * 
/******************************************************************************/

module led_top1(    
    seg    
    );
output  [11:0]  seg     ;
wire    [6:0]   led     ;

hex2led_common_cathode hex2led_inst (
    .hex(4'h8), 
    .led(led)
    ) ;            

led2seg led2seg_inst(
    .seg    (seg),
    .led    (led),
    .segcode(5'b11100) 
    );

endmodule