led_top3.v

来自「使用FPGA控制数码管,在数码管上动态的显示数字,很使用,可以直接作为其他模块的」· Verilog 代码 · 共 51 行

////////////////////////////////////////////////////////////////////////////////
// *****************************************************************************
// *  RICHIC CONFIDENTIAL PROPRIETARY NOTE                                     *
// *                                                                           *
// *  This software contains information confidential and proprietary to       *
// *  RicHic Inc.It shall not be reproduced in whole or in part or transferred *
// *  to other documents, or disclosed to third parties, or used for any       *
// *  purpose other than that for which it was obtained, without the prior     *
// *  written consent of RicHic Inc.                                           *
// *             (c) 2003, 2004, 2005 RicHic Inc.                              *
// *                All rights reserved                                        * 
/******************************************************************************/
//  这个示例中有一个明显违反编程规范的地方请检查！违反这个规范的结果请使用
//  开发系统进行测试

module led_top3(
    seg,    
    clk,
    rst_n // synthesis attribute clock_buffer of rst_n is ibufg;
    );

input               clk;
input               rst_n; 
output  [11:0]      seg ;

wire    [6 :0]      led ;
wire    [4 :0]      segcode;
wire    [3 :0]      hex;
  dynamic_hex3 dynamic_hex_inst(
    .hex    (hex),
    .segcode(segcode),
    
    .clk    (clk    ),
    .rst_n  (rst_n  ),
    .data   (16'h1234),
    .dot    (4'b0000)
    );

  hex2led_common_cathode hex2led_inst (
    .hex(hex), 
    .led(led)
    ) ;            
                
  led2seg led2seg_inst(
    .seg    (seg),
    .led    (led),
    .segcode(segcode) 
    );

endmodule