f26b.vhd

dds信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity f26b is
port(q1:in std_logic;
     m:in std_logic_vector(29 downto 0);
     f26b:buffer std_logic_vector(29 downto 0));
end;
architecture one of f26b is
begin
process(q1,m)
begin
   if q1='0' then f26b<=m;
    else f26b<="000010001000100010001000100010";
    end if;
end process;
end;