top.rpt

dds信号发生器

Project Information                                             f:\sin\top.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/04/2006 17:41:30

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

top       EPF10K20TC144-4  7      30     0    1024      8  %    1034     89 %

User Pins:                 7      30     0  



Project Information                                             f:\sin\top.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

top@125                           clk
top@8                             clk0
top@9                             clk1
top@10                            clk2
top@12                            clk3
top@13                            clk4
top@17                            clk5
top@41                            dot0
top@42                            dot1
top@65                            dot2
top@67                            dot3
top@68                            dot4
top@69                            dot5
top@70                            dot6
top@72                            dot7
top@73                            f0
top@78                            f1
top@79                            f2
top@80                            f3
top@81                            f4
top@82                            f5
top@83                            f6
top@86                            f7
top@87                            f8
top@88                            f9
top@89                            f10
top@90                            f11
top@91                            f12
top@92                            f13
top@95                            f14
top@96                            f15
top@36                            maot0
top@37                            maot1
top@38                            maot2
top@39                            maot3
top@30                            q0
top@31                            q1


Project Information                                             f:\sin\top.rpt

** EMBEDDED ARRAYS **


|zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|content: MEMORY (
               width        =    8;
               depth        =   64;
               segmentsize  =   64;
               mode         = MEM_READONLY#MEM_INITIALIZED;
               file         = "f:\sin\sinrom2.mif";
         )
         OF SEGMENTS (
               |zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|segment0_7,
               |zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|segment0_6,
               |zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|segment0_5,
               |zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|segment0_4,
               |zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|segment0_3,
               |zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|segment0_2,
               |zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|segment0_1,
               |zaibo:24|sinrom2:1|LPM_ROM:3|altrom:srom|segment0_0
);



|sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|content: MEMORY (
               width        =    8;
               depth        =   64;
               segmentsize  =   64;
               mode         = MEM_READONLY#MEM_INITIALIZED;
               file         = "f:\sin\sinrom1.mif";
         )
         OF SEGMENTS (
               |sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|segment0_7,
               |sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|segment0_6,
               |sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|segment0_5,
               |sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|segment0_4,
               |sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|segment0_3,
               |sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|segment0_2,
               |sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|segment0_1,
               |sin:30|sinrom1:25|LPM_ROM:4|altrom:srom|segment0_0
);




Project Information                                             f:\sin\top.rpt

** FILE HIERARCHY **



|control:4|
|qout:5|
|qout:5|lpm_add_sub:12|
|qout:5|lpm_add_sub:12|addcore:adder|
|qout:5|lpm_add_sub:12|altshift:result_ext_latency_ffs|
|qout:5|lpm_add_sub:12|altshift:carry_ext_latency_ffs|
|qout:5|lpm_add_sub:12|altshift:oflow_ext_latency_ffs|
|am:14|
|am:14|addq1:2|
|am:14|add8b:3|
|am:14|add8b:3|lpm_add_sub:25|
|am:14|add8b:3|lpm_add_sub:25|addcore:adder|
|am:14|add8b:3|lpm_add_sub:25|altshift:result_ext_latency_ffs|
|am:14|add8b:3|lpm_add_sub:25|altshift:carry_ext_latency_ffs|
|am:14|add8b:3|lpm_add_sub:25|altshift:oflow_ext_latency_ffs|
|am:14|mulma:5|
|am:14|mulma:5|lpm_mult:13|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:result_ext_latency_ffs|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:carry_ext_latency_ffs|
|am:14|mulma:5|lpm_mult:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:oflow_ext_latency_ffs|
|am:14|mulma:5|lpm_mult:13|altshift:external_latency_ffs|
|am:14|mulma:5|divide:17|
|am:14|mulma:5|divide:17|lpm_add_sub:59|
|am:14|mulma:5|divide:17|lpm_add_sub:59|addcore:adder|
|am:14|mulma:5|divide:17|lpm_add_sub:59|altshift:result_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:59|altshift:carry_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:59|altshift:oflow_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:81|
|am:14|mulma:5|divide:17|lpm_add_sub:81|addcore:adder|
|am:14|mulma:5|divide:17|lpm_add_sub:81|altshift:result_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:81|altshift:carry_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:81|altshift:oflow_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:106|
|am:14|mulma:5|divide:17|lpm_add_sub:106|addcore:adder|
|am:14|mulma:5|divide:17|lpm_add_sub:106|altshift:result_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:106|altshift:carry_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:106|altshift:oflow_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:131|
|am:14|mulma:5|divide:17|lpm_add_sub:131|addcore:adder|
|am:14|mulma:5|divide:17|lpm_add_sub:131|altshift:result_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:131|altshift:carry_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:131|altshift:oflow_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:156|
|am:14|mulma:5|divide:17|lpm_add_sub:156|addcore:adder|
|am:14|mulma:5|divide:17|lpm_add_sub:156|altshift:result_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:156|altshift:carry_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:156|altshift:oflow_ext_latency_ffs|
|am:14|mulma:5|divide:17|lpm_add_sub:181|
|am:14|mulma:5|divide:17|lpm_add_sub:181|addcore:adder|