📄 mulma.rpt
字号:
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 15/96 ( 15%)
Total logic cells used: 98/1728 ( 5%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.57/4 ( 89%)
Total fan-in: 350/6912 ( 5%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 98
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 19/1728 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 0 8 0 0 8 8 0 0 0 2 0 0 8 58/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 0 8 0 0 8 0 0 0 0 0 0 0 0 8 40/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 8 8 8 8 0 8 8 8 0 0 0 2 0 0 16 98/0
Device-Specific Information: e:\edashi\am\mulma.rpt
mulma
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
10 - - B -- INPUT ^ 0 0 0 7 fout0
130 - - - 22 INPUT ^ 0 0 0 9 fout1
125 - - - -- INPUT ^ 0 0 0 10 fout2
99 - - B -- INPUT ^ 0 0 0 10 fout3
49 - - - 21 INPUT ^ 0 0 0 10 fout4
141 - - - 33 INPUT ^ 0 0 0 10 fout5
55 - - - -- INPUT ^ 0 0 0 10 fout6
96 - - C -- INPUT ^ 0 0 0 7 fout7
124 - - - -- INPUT ^ 0 0 0 20 ma0
56 - - - -- INPUT ^ 0 0 0 23 ma1
54 - - - -- INPUT ^ 0 0 0 16 ma2
126 - - - -- INPUT ^ 0 0 0 16 ma3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\edashi\am\mulma.rpt
mulma
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
46 - - - 27 OUTPUT 0 1 0 0 q10
98 - - B -- OUTPUT 0 1 0 0 q11
44 - - - 29 OUTPUT 0 1 0 0 q12
9 - - B -- OUTPUT 0 1 0 0 q13
37 - - - 35 OUTPUT 0 1 0 0 q14
133 - - - 28 OUTPUT 0 1 0 0 q15
13 - - C -- OUTPUT 0 1 0 0 q16
18 - - C -- OUTPUT 0 1 0 0 q17
12 - - C -- OUTPUT 0 1 0 0 q18
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\edashi\am\mulma.rpt
mulma
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 19 OR2 0 4 1 0 |DIVIDE:17|lpm_add_sub:59|addcore:adder|:63
- 6 - C 24 OR2 0 4 1 3 |DIVIDE:17|lpm_add_sub:81|addcore:adder|pcarry4
- 3 - C 27 OR2 0 4 1 3 |DIVIDE:17|lpm_add_sub:106|addcore:adder|pcarry4
- 4 - C 27 OR2 0 4 1 3 |DIVIDE:17|lpm_add_sub:131|addcore:adder|pcarry4
- 8 - B 36 OR2 0 4 1 3 |DIVIDE:17|lpm_add_sub:156|addcore:adder|pcarry4
- 2 - B 36 OR2 0 4 1 3 |DIVIDE:17|lpm_add_sub:181|addcore:adder|pcarry4
- 4 - B 29 OR2 0 4 1 3 |DIVIDE:17|lpm_add_sub:206|addcore:adder|pcarry4
- 5 - B 28 OR2 0 4 1 3 |DIVIDE:17|lpm_add_sub:231|addcore:adder|pcarry4
- 6 - B 28 OR2 0 4 1 0 |DIVIDE:17|lpm_add_sub:256|addcore:adder|pcarry4
- 8 - C 24 LCELL 0 3 0 4 |DIVIDE:17|StageOut0_0
- 7 - C 24 LCELL 0 4 0 3 |DIVIDE:17|StageOut0_1
- 4 - C 19 LCELL 0 4 0 2 |DIVIDE:17|StageOut0_2
- 5 - C 24 LCELL 0 4 0 1 |DIVIDE:17|StageOut0_3
- 5 - C 27 LCELL 0 3 0 4 |DIVIDE:17|StageOut1_0
- 1 - C 24 LCELL 0 2 0 3 |DIVIDE:17|StageOut1_1
- 2 - C 24 LCELL 0 3 0 2 |DIVIDE:17|StageOut1_2
- 3 - C 24 LCELL 0 4 0 1 |DIVIDE:17|StageOut1_3
- 2 - B 23 LCELL 0 3 0 4 |DIVIDE:17|StageOut2_0
- 7 - C 27 LCELL 0 2 0 3 |DIVIDE:17|StageOut2_1
- 8 - C 27 LCELL 0 3 0 2 |DIVIDE:17|StageOut2_2
- 6 - C 27 LCELL 0 4 0 1 |DIVIDE:17|StageOut2_3
- 6 - B 36 LCELL 0 3 0 4 |DIVIDE:17|StageOut3_0
- 5 - B 36 LCELL 0 2 0 3 |DIVIDE:17|StageOut3_1
- 2 - C 27 LCELL 0 3 0 2 |DIVIDE:17|StageOut3_2
- 1 - C 27 LCELL 0 4 0 1 |DIVIDE:17|StageOut3_3
- 1 - B 22 LCELL 0 4 0 4 |DIVIDE:17|StageOut4_0
- 1 - B 36 LCELL 0 2 0 3 |DIVIDE:17|StageOut4_1
- 3 - B 36 LCELL 0 3 0 2 |DIVIDE:17|StageOut4_2
- 7 - B 36 LCELL 0 4 0 1 |DIVIDE:17|StageOut4_3
- 8 - B 29 LCELL 0 2 0 4 |DIVIDE:17|StageOut5_0
- 6 - B 29 LCELL 0 2 0 3 |DIVIDE:17|StageOut5_1
- 7 - B 29 LCELL 0 3 0 2 |DIVIDE:17|StageOut5_2
- 5 - B 29 LCELL 0 4 0 1 |DIVIDE:17|StageOut5_3
- 2 - B 28 LCELL 2 2 0 4 |DIVIDE:17|StageOut6_0
- 2 - B 29 LCELL 0 2 0 3 |DIVIDE:17|StageOut6_1
- 3 - B 29 LCELL 0 3 0 2 |DIVIDE:17|StageOut6_2
- 1 - B 29 LCELL 0 4 0 1 |DIVIDE:17|StageOut6_3
- 8 - B 28 LCELL 4 0 0 1 |DIVIDE:17|StageOut7_0
- 4 - B 28 LCELL 0 2 0 1 |DIVIDE:17|StageOut7_1
- 7 - B 28 LCELL 0 3 0 1 |DIVIDE:17|StageOut7_2
- 3 - B 28 LCELL 0 4 0 1 |DIVIDE:17|StageOut7_3
- 2 - B 22 OR2 2 2 0 3 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:108
- 8 - B 22 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:109
- 3 - B 23 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:110
- 8 - B 23 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:111
- 3 - C 20 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:112
- 2 - C 36 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:113
- 5 - C 19 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:114
- 1 - B 28 OR2 2 2 0 3 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:120
- 6 - B 22 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:225
- 4 - B 22 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:226
- 6 - B 23 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:227
- 4 - B 23 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:228
- 2 - C 20 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:229
- 7 - C 36 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:230
- 8 - C 19 AND2 s 3 1 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~231~1
- 1 - C 19 OR2 1 3 0 4 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:231
- 1 - B 33 OR2 s 4 0 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~101~1
- 2 - B 25 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~102~1
- 5 - B 22 OR2 2 1 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:102
- 3 - B 25 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~103~1
- 5 - B 25 OR2 2 1 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:103
- 2 - B 21 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~104~1
- 5 - B 23 OR2 2 1 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:104
- 8 - B 21 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~105~1
- 4 - B 21 OR2 2 1 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:105
- 7 - C 20 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~106~1
- 8 - C 20 OR2 2 1 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:106
- 3 - C 36 OR2 4 0 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:107
- 2 - B 33 AND2 4 0 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:112
- 7 - C 19 AND2 4 0 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:203
- 6 - B 21 AND2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~209~1
- 7 - B 21 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~209~2
- 5 - B 21 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:209
- 6 - B 25 AND2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~210~1
- 8 - B 25 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~210~2
- 7 - B 22 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:210
- 4 - B 25 AND2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~211~1
- 7 - B 25 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~211~2
- 1 - B 25 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:211
- 1 - B 21 AND2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~212~1
- 3 - B 21 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~212~2
- 7 - B 23 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:212
- 4 - C 20 AND2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~213~1
- 5 - C 20 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~213~2
- 6 - C 20 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:213
- 4 - C 36 AND2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~214~1
- 5 - C 36 OR2 s 4 0 0 1 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|~214~2
- 6 - C 36 OR2 2 2 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|csa_cell:adder0|:214
- 3 - B 22 OR2 0 4 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry4
- 4 - B 36 OR2 0 3 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry5
- 1 - B 23 OR2 0 3 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry6
- 1 - C 20 OR2 0 3 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry7
- 4 - C 24 OR2 0 3 0 2 |LPM_MULT:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry8
- 1 - C 36 OR2 0 3 0 4 |LPM_MULT:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry9
- 8 - C 36 OR2 0 3 0 4 |LPM_MULT:13|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:168
- 6 - C 19 AND2 2 0 0 3 |LPM_MULT:13|multcore:mult_core|decoder_node2_7
- 3 - C 19 AND2 2 0 0 4 |LPM_MULT:13|multcore:mult_core|decoder_node3_7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\edashi\am\mulma.rpt
mulma
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
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