📄 addq1.srr

📁 dds信号发生器

💻 SRR

字号:

Synplify VHDL Compiler, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved

@E:"e:\edashi\am\addq1.vhd":12:11:12:12|No identifier "addq1" in scope
1 error parsing file e:\edashi\am\addq1.vhd
@END
Process took 0 seconds realtime, 0.015 seconds cputime

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