addq1.srr

来自「dds信号发生器」· SRR 代码 · 共 8 行

Synplify VHDL Compiler, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved

@E:"e:\edashi\am\addq1.vhd":12:11:12:12|No identifier "addq1" in scope
1 error parsing file e:\edashi\am\addq1.vhd
@END
Process took 0 seconds realtime, 0.015 seconds cputime