reg8b.vhd

来自「dds信号发生器」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
entity REG6B is 
  port(CLK:in std_logic;
       DIN:in std_logic_vector(5 downto 0);
    DOUT:out std_logic_vector(5 downto 0));
end;
architecture ONE of REG6B is
begin
  process(CLk)
  begin
    if CLK'event and CLK='1'then 
     DOUT<=DIN;
    end if;
  end process;
end;