f26b.rpt

dds信号发生器

f26b24   =  _LC2_A1;

-- Node name is 'f26b25' 
-- Equation name is 'f26b25', type is output 
f26b25   =  _LC3_C3;

-- Node name is 'f26b26' 
-- Equation name is 'f26b26', type is output 
f26b26   =  _LC5_C3;

-- Node name is 'f26b27' 
-- Equation name is 'f26b27', type is output 
f26b27   =  _LC7_B10;

-- Node name is 'f26b28' 
-- Equation name is 'f26b28', type is output 
f26b28   =  _LC6_A14;

-- Node name is 'f26b29' 
-- Equation name is 'f26b29', type is output 
f26b29   =  _LC2_B10;

-- Node name is ':316' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = LCELL( _EQ001);
  _EQ001 =  m29 & !q1;

-- Node name is ':322' 
-- Equation name is '_LC6_A14', type is buried 
_LC6_A14 = LCELL( _EQ002);
  _EQ002 =  m28 & !q1;

-- Node name is ':328' 
-- Equation name is '_LC7_B10', type is buried 
_LC7_B10 = LCELL( _EQ003);
  _EQ003 =  m27 & !q1;

-- Node name is ':334' 
-- Equation name is '_LC5_C3', type is buried 
_LC5_C3  = LCELL( _EQ004);
  _EQ004 =  m26 & !q1;

-- Node name is ':339' 
-- Equation name is '_LC3_C3', type is buried 
_LC3_C3  = LCELL( _EQ005);
  _EQ005 =  m25
         #  q1;

-- Node name is ':346' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = LCELL( _EQ006);
  _EQ006 =  m24 & !q1;

-- Node name is ':352' 
-- Equation name is '_LC2_A14', type is buried 
_LC2_A14 = LCELL( _EQ007);
  _EQ007 =  m23 & !q1;

-- Node name is ':358' 
-- Equation name is '_LC8_C3', type is buried 
_LC8_C3  = LCELL( _EQ008);
  _EQ008 =  m22 & !q1;

-- Node name is ':363' 
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = LCELL( _EQ009);
  _EQ009 =  m21
         #  q1;

-- Node name is ':370' 
-- Equation name is '_LC5_B10', type is buried 
_LC5_B10 = LCELL( _EQ010);
  _EQ010 =  m20 & !q1;

-- Node name is ':376' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = LCELL( _EQ011);
  _EQ011 =  m19 & !q1;

-- Node name is ':382' 
-- Equation name is '_LC4_B10', type is buried 
_LC4_B10 = LCELL( _EQ012);
  _EQ012 =  m18 & !q1;

-- Node name is ':387' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = LCELL( _EQ013);
  _EQ013 =  m17
         #  q1;

-- Node name is ':394' 
-- Equation name is '_LC5_A14', type is buried 
_LC5_A14 = LCELL( _EQ014);
  _EQ014 =  m16 & !q1;

-- Node name is ':400' 
-- Equation name is '_LC4_C3', type is buried 
_LC4_C3  = LCELL( _EQ015);
  _EQ015 =  m15 & !q1;

-- Node name is ':406' 
-- Equation name is '_LC4_A14', type is buried 
_LC4_A14 = LCELL( _EQ016);
  _EQ016 =  m14 & !q1;

-- Node name is ':411' 
-- Equation name is '_LC8_B10', type is buried 
_LC8_B10 = LCELL( _EQ017);
  _EQ017 =  m13
         #  q1;

-- Node name is ':418' 
-- Equation name is '_LC7_C3', type is buried 
_LC7_C3  = LCELL( _EQ018);
  _EQ018 =  m12 & !q1;

-- Node name is ':424' 
-- Equation name is '_LC1_A14', type is buried 
_LC1_A14 = LCELL( _EQ019);
  _EQ019 =  m11 & !q1;

-- Node name is ':430' 
-- Equation name is '_LC6_A1', type is buried 
_LC6_A1  = LCELL( _EQ020);
  _EQ020 =  m10 & !q1;

-- Node name is ':435' 
-- Equation name is '_LC1_C3', type is buried 
_LC1_C3  = LCELL( _EQ021);
  _EQ021 =  m9
         #  q1;

-- Node name is ':442' 
-- Equation name is '_LC6_B10', type is buried 
_LC6_B10 = LCELL( _EQ022);
  _EQ022 =  m8 & !q1;

-- Node name is ':448' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ023);
  _EQ023 =  m7 & !q1;

-- Node name is ':454' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ024);
  _EQ024 =  m6 & !q1;

-- Node name is ':459' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ025);
  _EQ025 =  m5
         #  q1;

-- Node name is ':466' 
-- Equation name is '_LC7_A1', type is buried 
_LC7_A1  = LCELL( _EQ026);
  _EQ026 =  m4 & !q1;

-- Node name is ':472' 
-- Equation name is '_LC3_B10', type is buried 
_LC3_B10 = LCELL( _EQ027);
  _EQ027 =  m3 & !q1;

-- Node name is ':478' 
-- Equation name is '_LC3_A14', type is buried 
_LC3_A14 = LCELL( _EQ028);
  _EQ028 =  m2 & !q1;

-- Node name is ':483' 
-- Equation name is '_LC8_A1', type is buried 
_LC8_A1  = LCELL( _EQ029);
  _EQ029 =  m1
         #  q1;

-- Node name is ':490' 
-- Equation name is '_LC7_A14', type is buried 
_LC7_A14 = LCELL( _EQ030);
  _EQ030 =  m0 & !q1;



Project Information                                            f:\sin\f26b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 26,178K