add128.vhd

来自「dds信号发生器」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add128 is
port(q4:in std_logic_vector(7 downto 0);
     amout:out std_logic_vector(7 downto 0));
end;
architecture one of add128 is
begin
amout<=q4+"10000000";
end;