📄 nzhi.rpt
字号:
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\sin\nzhi.rpt
nzhi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\sin\nzhi.rpt
nzhi
** EQUATIONS **
-- Node name is 'n0'
-- Equation name is 'n0', type is output
n0 = GND;
-- Node name is 'n1'
-- Equation name is 'n1', type is output
n1 = GND;
-- Node name is 'n2'
-- Equation name is 'n2', type is output
n2 = GND;
-- Node name is 'n3'
-- Equation name is 'n3', type is output
n3 = GND;
-- Node name is 'n4'
-- Equation name is 'n4', type is output
n4 = GND;
-- Node name is 'n5'
-- Equation name is 'n5', type is output
n5 = GND;
-- Node name is 'n6'
-- Equation name is 'n6', type is output
n6 = GND;
-- Node name is 'n7'
-- Equation name is 'n7', type is output
n7 = GND;
-- Node name is 'n8'
-- Equation name is 'n8', type is output
n8 = GND;
-- Node name is 'n9'
-- Equation name is 'n9', type is output
n9 = GND;
-- Node name is 'n10'
-- Equation name is 'n10', type is output
n10 = GND;
-- Node name is 'n11'
-- Equation name is 'n11', type is output
n11 = GND;
-- Node name is 'n12'
-- Equation name is 'n12', type is output
n12 = GND;
-- Node name is 'n13'
-- Equation name is 'n13', type is output
n13 = GND;
-- Node name is 'n14'
-- Equation name is 'n14', type is output
n14 = GND;
-- Node name is 'n15'
-- Equation name is 'n15', type is output
n15 = GND;
-- Node name is 'n16'
-- Equation name is 'n16', type is output
n16 = GND;
-- Node name is 'n17'
-- Equation name is 'n17', type is output
n17 = GND;
-- Node name is 'n18'
-- Equation name is 'n18', type is output
n18 = GND;
-- Node name is 'n19'
-- Equation name is 'n19', type is output
n19 = GND;
-- Node name is 'n20'
-- Equation name is 'n20', type is output
n20 = GND;
-- Node name is 'n21'
-- Equation name is 'n21', type is output
n21 = GND;
-- Node name is 'n22'
-- Equation name is 'n22', type is output
n22 = GND;
-- Node name is 'n23'
-- Equation name is 'n23', type is output
n23 = GND;
-- Node name is 'n24'
-- Equation name is 'n24', type is output
n24 = GND;
-- Node name is 'n25'
-- Equation name is 'n25', type is output
n25 = GND;
-- Node name is 'n26'
-- Equation name is 'n26', type is output
n26 = VCC;
Project Information f:\sin\nzhi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 22,121K
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