zhi.vhd

来自「dds信号发生器」· VHDL 代码 · 共 11 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zhi is
port(n:out std_logic_vector(10 downto 0));
end;
architecture one of zhi is
begin
n<="11101010011";
end;