📄 addq1.rpt
字号:
addq1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 4/144( 2%) 6/ 72( 8%) 0/ 72( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\edashi\am\addq1.rpt
addq1
** EQUATIONS **
ma0 : INPUT;
ma1 : INPUT;
ma2 : INPUT;
ma3 : INPUT;
-- Node name is 'maout0'
-- Equation name is 'maout0', type is output
maout0 = _LC8_F16;
-- Node name is 'maout1'
-- Equation name is 'maout1', type is output
maout1 = _LC1_F16;
-- Node name is 'maout2'
-- Equation name is 'maout2', type is output
maout2 = _LC1_F8;
-- Node name is 'maout3'
-- Equation name is 'maout3', type is output
maout3 = _LC2_F8;
-- Node name is 'maout4'
-- Equation name is 'maout4', type is output
maout4 = _LC8_F8;
-- Node name is 'maout5'
-- Equation name is 'maout5', type is output
maout5 = _LC6_F16;
-- Node name is 'maout6'
-- Equation name is 'maout6', type is output
maout6 = _LC4_F8;
-- Node name is 'maout7'
-- Equation name is 'maout7', type is output
maout7 = _LC6_F8;
-- Node name is ':366'
-- Equation name is '_LC4_F16', type is buried
!_LC4_F16 = _LC4_F16~NOT;
_LC4_F16~NOT = LCELL( _EQ001);
_EQ001 = ma2
# !ma0
# !ma1
# ma3;
-- Node name is ':378'
-- Equation name is '_LC5_F16', type is buried
!_LC5_F16 = _LC5_F16~NOT;
_LC5_F16~NOT = LCELL( _EQ002);
_EQ002 = !ma1
# ma3
# ma0
# ma2;
-- Node name is ':390'
-- Equation name is '_LC2_F16', type is buried
_LC2_F16 = LCELL( _EQ003);
_EQ003 = ma0 & !ma1 & !ma2 & !ma3;
-- Node name is ':402'
-- Equation name is '_LC5_F8', type is buried
_LC5_F8 = LCELL( _EQ004);
_EQ004 = !ma0 & !ma1 & !ma2 & !ma3;
-- Node name is ':405'
-- Equation name is '_LC6_F8', type is buried
_LC6_F8 = LCELL( _EQ005);
_EQ005 = !ma0 & !ma1 & !ma3
# !ma2 & !ma3;
-- Node name is ':438'
-- Equation name is '_LC4_F8', type is buried
_LC4_F8 = LCELL( _EQ006);
_EQ006 = !ma0 & ma1 & !ma3
# ma0 & ma2 & !ma3
# ma0 & !ma1 & !ma3
# !ma0 & !ma2 & !ma3;
-- Node name is ':470'
-- Equation name is '_LC3_F8', type is buried
_LC3_F8 = LCELL( _EQ007);
_EQ007 = ma0 & ma1 & !ma2 & !ma3
# ma0 & !ma1 & ma2 & !ma3
# !ma0 & ma1 & ma2 & !ma3
# !ma0 & !ma1 & !ma2 & ma3;
-- Node name is ':471'
-- Equation name is '_LC6_F16', type is buried
_LC6_F16 = LCELL( _EQ008);
_EQ008 = _LC2_F16
# _LC5_F8
# _LC3_F8;
-- Node name is ':504'
-- Equation name is '_LC8_F8', type is buried
_LC8_F8 = LCELL( _EQ009);
_EQ009 = ma0 & ma1 & !ma2 & !ma3
# !ma0 & !ma1 & !ma3
# !ma1 & ma2 & !ma3
# !ma0 & !ma1 & !ma2
# !ma1 & !ma2 & ma3;
-- Node name is ':537'
-- Equation name is '_LC2_F8', type is buried
_LC2_F8 = LCELL( _EQ010);
_EQ010 = !ma0 & !ma2 & !ma3
# !ma0 & !ma1 & !ma3
# !ma1 & ma2 & !ma3
# ma0 & ma2 & !ma3
# ma0 & !ma1 & !ma2 & ma3;
-- Node name is ':570'
-- Equation name is '_LC1_F8', type is buried
_LC1_F8 = LCELL( _EQ011);
_EQ011 = !ma1 & !ma2 & !ma3
# !ma0 & !ma2 & !ma3
# ma0 & !ma1 & !ma3
# !ma0 & ma1 & !ma3
# ma0 & ma2 & !ma3;
-- Node name is ':603'
-- Equation name is '_LC1_F16', type is buried
_LC1_F16 = LCELL( _EQ012);
_EQ012 = !_LC2_F16 & _LC3_F8
# _LC5_F8;
-- Node name is ':624'
-- Equation name is '_LC7_F16', type is buried
_LC7_F16 = LCELL( _EQ013);
_EQ013 = !ma1 & ma2 & !ma3
# !ma1 & !ma2 & ma3;
-- Node name is '~636~1'
-- Equation name is '~636~1', location is LC3_F16, type is buried.
-- synthesized logic cell
_LC3_F16 = LCELL( _EQ014);
_EQ014 = _LC2_F16
# _LC5_F8;
-- Node name is ':636'
-- Equation name is '_LC8_F16', type is buried
_LC8_F16 = LCELL( _EQ015);
_EQ015 = _LC3_F16
# !_LC4_F16 & !_LC5_F16 & _LC7_F16;
Project Information e:\edashi\am\addq1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 28,198K
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