cnt300.vhd

来自「dds信号发生器」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt300 is
port(clk:in std_logic;
     clk10k:out std_logic);
end;
architecture one of cnt300 is 
signal cnt:std_logic_vector(8 downto 0);
begin
process(clk)
begin
   if clk'event and clk='1' then 
       if cnt="100101011" then cnt<="000000000";
        else cnt<=cnt+'1';
        end if;
    end if;
end process;
process(cnt)
begin
   if cnt="100101011" then clk10k<='1';
    else clk10k<='0';
    end if;
   end process;
end;