codeout.rpt

dds信号发生器

-- Node name is '|delay:16|:5' 
-- Equation name is '_LC2_E11', type is buried 
_LC2_E11 = DFFE( _LC3_D1, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:6' 
-- Equation name is '_LC3_E11', type is buried 
_LC3_E11 = DFFE( _LC2_E11, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:8' 
-- Equation name is '_LC4_E11', type is buried 
_LC4_E11 = DFFE( _LC3_E11, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:9' 
-- Equation name is '_LC5_E11', type is buried 
_LC5_E11 = DFFE( _LC4_E11, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:10' 
-- Equation name is '_LC1_E11', type is buried 
_LC1_E11 = DFFE( _LC5_E11, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:11' 
-- Equation name is '_LC2_E22', type is buried 
_LC2_E22 = DFFE( _LC1_E11, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:12' 
-- Equation name is '_LC3_E22', type is buried 
_LC3_E22 = DFFE( _LC2_E22, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:13' 
-- Equation name is '_LC4_E22', type is buried 
_LC4_E22 = DFFE( _LC3_E22, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:14' 
-- Equation name is '_LC5_E22', type is buried 
_LC5_E22 = DFFE( _LC4_E22, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:15' 
-- Equation name is '_LC6_E22', type is buried 
_LC6_E22 = DFFE( _LC5_E22, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:16' 
-- Equation name is '_LC7_E22', type is buried 
_LC7_E22 = DFFE( _LC6_E22, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:17' 
-- Equation name is '_LC1_E22', type is buried 
_LC1_E22 = DFFE( _LC7_E22, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:18' 
-- Equation name is '_LC2_E21', type is buried 
_LC2_E21 = DFFE( _LC1_E22, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:22' 
-- Equation name is '_LC4_E25', type is buried 
_LC4_E25 = DFFE( _LC3_E25, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:23' 
-- Equation name is '_LC3_E25', type is buried 
_LC3_E25 = DFFE( _LC2_E25, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:24' 
-- Equation name is '_LC2_E25', type is buried 
_LC2_E25 = DFFE( _LC1_E33, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:25' 
-- Equation name is '_LC1_E33', type is buried 
_LC1_E33 = DFFE( _LC6_E33, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:26' 
-- Equation name is '_LC6_E33', type is buried 
_LC6_E33 = DFFE( _LC5_E33, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:27' 
-- Equation name is '_LC5_E33', type is buried 
_LC5_E33 = DFFE( _LC4_E33, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:28' 
-- Equation name is '_LC4_E33', type is buried 
_LC4_E33 = DFFE( _LC3_E33, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:29' 
-- Equation name is '_LC3_E33', type is buried 
_LC3_E33 = DFFE( _LC2_E33, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:30' 
-- Equation name is '_LC2_E33', type is buried 
_LC2_E33 = DFFE( _LC1_E21, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:31' 
-- Equation name is '_LC1_E21', type is buried 
_LC1_E21 = DFFE( _LC6_E21, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:32' 
-- Equation name is '_LC6_E21', type is buried 
_LC6_E21 = DFFE( _LC5_E21, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:33' 
-- Equation name is '_LC5_E21', type is buried 
_LC5_E21 = DFFE( _LC4_E21, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:34' 
-- Equation name is '_LC4_E21', type is buried 
_LC4_E21 = DFFE( _LC3_E21, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:35' 
-- Equation name is '_LC3_E21', type is buried 
_LC3_E21 = DFFE( _LC2_E21, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:39' 
-- Equation name is '_LC5_E27', type is buried 
_LC5_E27 = DFFE( _LC4_E27, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:40' 
-- Equation name is '_LC4_E27', type is buried 
_LC4_E27 = DFFE( _LC2_E29, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:41' 
-- Equation name is '_LC2_E29', type is buried 
_LC2_E29 = DFFE( _LC8_E29, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:42' 
-- Equation name is '_LC8_E29', type is buried 
_LC8_E29 = DFFE( _LC7_E29, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:43' 
-- Equation name is '_LC7_E29', type is buried 
_LC7_E29 = DFFE( _LC6_E29, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:44' 
-- Equation name is '_LC6_E29', type is buried 
_LC6_E29 = DFFE( _LC5_E29, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:45' 
-- Equation name is '_LC5_E29', type is buried 
_LC5_E29 = DFFE( _LC4_E29, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:46' 
-- Equation name is '_LC4_E29', type is buried 
_LC4_E29 = DFFE( _LC3_E29, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:47' 
-- Equation name is '_LC3_E29', type is buried 
_LC3_E29 = DFFE( _LC1_E29, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:48' 
-- Equation name is '_LC1_E29', type is buried 
_LC1_E29 = DFFE( _LC1_E25, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:49' 
-- Equation name is '_LC1_E25', type is buried 
_LC1_E25 = DFFE( _LC6_E25, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:50' 
-- Equation name is '_LC6_E25', type is buried 
_LC6_E25 = DFFE( _LC5_E25, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is '|delay:16|:51' 
-- Equation name is '_LC5_E25', type is buried 
_LC5_E25 = DFFE( _LC4_E25, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':4' 
-- Equation name is '_LC2_E27', type is buried 
_LC2_E27 = DFFE( _EQ017,  _LC6_E27,  VCC,  VCC,  VCC);
  _EQ017 =  _LC1_E27 &  _LC3_E27
         # !_LC1_E27 & !_LC3_E27;

-- Node name is ':5' 
-- Equation name is '_LC3_E27', type is buried 
_LC3_E27 = DFFE(!_LC2_E27,  _LC6_E27,  VCC,  VCC,  VCC);

-- Node name is ':6' 
-- Equation name is '_LC7_E27', type is buried 
_LC7_E27 = DFFE( _LC3_E27,  _LC6_E27,  VCC,  VCC,  VCC);

-- Node name is ':7' 
-- Equation name is '_LC1_E27', type is buried 
_LC1_E27 = DFFE( _LC8_E27,  _LC6_E27,  VCC,  VCC,  VCC);

-- Node name is ':8' 
-- Equation name is '_LC8_E27', type is buried 
_LC8_E27 = DFFE( _LC7_E27,  _LC6_E27,  VCC,  VCC,  VCC);



Project Information                                         f:\sin\codeout.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KE' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 36,230K