📄 codeout.rpt
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Device-Specific Information: f:\sin\codeout.rpt
codeout
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - D 01 AND2 0 3 0 1 |CNT300:15|LPM_ADD_SUB:104|addcore:adder|:79
- 1 - D 01 AND2 0 4 0 3 |CNT300:15|LPM_ADD_SUB:104|addcore:adder|:83
- 1 - D 09 AND2 0 3 0 3 |CNT300:15|LPM_ADD_SUB:104|addcore:adder|:91
- 6 - D 09 AND2 0 2 0 1 |CNT300:15|LPM_ADD_SUB:104|addcore:adder|:95
- 7 - D 09 DFFE + 0 3 0 1 |CNT300:15|cnt8 (|CNT300:15|:3)
- 5 - D 09 DFFE + 0 3 0 2 |CNT300:15|cnt7 (|CNT300:15|:4)
- 4 - D 09 DFFE + 0 2 0 3 |CNT300:15|cnt6 (|CNT300:15|:5)
- 3 - D 09 DFFE + 0 3 0 2 |CNT300:15|cnt5 (|CNT300:15|:6)
- 8 - D 09 DFFE + 0 2 0 3 |CNT300:15|cnt4 (|CNT300:15|:7)
- 6 - D 01 DFFE + 0 2 0 2 |CNT300:15|cnt3 (|CNT300:15|:8)
- 8 - D 01 DFFE + 0 3 0 4 |CNT300:15|cnt2 (|CNT300:15|:9)
- 7 - D 01 DFFE + 0 1 0 5 |CNT300:15|cnt1 (|CNT300:15|:10)
- 2 - D 08 DFFE + 0 0 0 6 |CNT300:15|cnt0 (|CNT300:15|:11)
- 2 - D 09 OR2 s 0 3 0 1 |CNT300:15|~49~1
- 4 - D 01 OR2 s 0 4 0 3 |CNT300:15|~49~2
- 2 - D 01 OR2 ! 0 4 0 6 |CNT300:15|:49
- 3 - D 01 DFFE + 0 4 0 1 |delay:16|:1
- 2 - E 11 DFFE + 0 1 0 1 |delay:16|:5
- 3 - E 11 DFFE + 0 1 0 1 |delay:16|:6
- 4 - E 11 DFFE + 0 1 0 1 |delay:16|:8
- 5 - E 11 DFFE + 0 1 0 1 |delay:16|:9
- 1 - E 11 DFFE + 0 1 0 1 |delay:16|:10
- 2 - E 22 DFFE + 0 1 0 1 |delay:16|:11
- 3 - E 22 DFFE + 0 1 0 1 |delay:16|:12
- 4 - E 22 DFFE + 0 1 0 1 |delay:16|:13
- 5 - E 22 DFFE + 0 1 0 1 |delay:16|:14
- 6 - E 22 DFFE + 0 1 0 1 |delay:16|:15
- 7 - E 22 DFFE + 0 1 0 1 |delay:16|:16
- 1 - E 22 DFFE + 0 1 0 1 |delay:16|:17
- 2 - E 21 DFFE + 0 1 0 1 |delay:16|:18
- 4 - E 25 DFFE + 0 1 0 1 |delay:16|:22
- 3 - E 25 DFFE + 0 1 0 1 |delay:16|:23
- 2 - E 25 DFFE + 0 1 0 1 |delay:16|:24
- 1 - E 33 DFFE + 0 1 0 1 |delay:16|:25
- 6 - E 33 DFFE + 0 1 0 1 |delay:16|:26
- 5 - E 33 DFFE + 0 1 0 1 |delay:16|:27
- 4 - E 33 DFFE + 0 1 0 1 |delay:16|:28
- 3 - E 33 DFFE + 0 1 0 1 |delay:16|:29
- 2 - E 33 DFFE + 0 1 0 1 |delay:16|:30
- 1 - E 21 DFFE + 0 1 0 1 |delay:16|:31
- 6 - E 21 DFFE + 0 1 0 1 |delay:16|:32
- 5 - E 21 DFFE + 0 1 0 1 |delay:16|:33
- 4 - E 21 DFFE + 0 1 0 1 |delay:16|:34
- 3 - E 21 DFFE + 0 1 0 1 |delay:16|:35
- 6 - E 27 DFFE + 0 1 0 5 |delay:16|clkout (|delay:16|:38)
- 5 - E 27 DFFE + 0 1 0 1 |delay:16|:39
- 4 - E 27 DFFE + 0 1 0 1 |delay:16|:40
- 2 - E 29 DFFE + 0 1 0 1 |delay:16|:41
- 8 - E 29 DFFE + 0 1 0 1 |delay:16|:42
- 7 - E 29 DFFE + 0 1 0 1 |delay:16|:43
- 6 - E 29 DFFE + 0 1 0 1 |delay:16|:44
- 5 - E 29 DFFE + 0 1 0 1 |delay:16|:45
- 4 - E 29 DFFE + 0 1 0 1 |delay:16|:46
- 3 - E 29 DFFE + 0 1 0 1 |delay:16|:47
- 1 - E 29 DFFE + 0 1 0 1 |delay:16|:48
- 1 - E 25 DFFE + 0 1 0 1 |delay:16|:49
- 6 - E 25 DFFE + 0 1 0 1 |delay:16|:50
- 5 - E 25 DFFE + 0 1 0 1 |delay:16|:51
- 2 - E 27 DFFE 0 3 0 1 :4
- 3 - E 27 DFFE 0 2 0 2 :5
- 7 - E 27 DFFE 0 2 0 1 :6
- 1 - E 27 DFFE 0 2 1 1 :7
- 8 - E 27 DFFE 0 2 0 1 :8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\sin\codeout.rpt
codeout
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 6/144( 4%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 7/144( 4%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\sin\codeout.rpt
codeout
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 51 clk
DFF 5 |delay:16|clkout
Device-Specific Information: f:\sin\codeout.rpt
codeout
** EQUATIONS **
clk : INPUT;
-- Node name is 'code'
-- Equation name is 'code', type is output
code = _LC1_E27;
-- Node name is '|CNT300:15|:11' = '|CNT300:15|cnt0'
-- Equation name is '_LC2_D8', type is buried
_LC2_D8 = DFFE(!_LC2_D8, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|CNT300:15|:10' = '|CNT300:15|cnt1'
-- Equation name is '_LC7_D1', type is buried
_LC7_D1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC2_D8 & !_LC7_D1
# !_LC2_D8 & _LC7_D1;
-- Node name is '|CNT300:15|:9' = '|CNT300:15|cnt2'
-- Equation name is '_LC8_D1', type is buried
_LC8_D1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC2_D8 & _LC8_D1
# !_LC7_D1 & _LC8_D1
# _LC2_D8 & _LC4_D1 & _LC7_D1 & !_LC8_D1;
-- Node name is '|CNT300:15|:8' = '|CNT300:15|cnt3'
-- Equation name is '_LC6_D1', type is buried
_LC6_D1 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC2_D1 & !_LC5_D1 & _LC6_D1
# !_LC2_D1 & _LC5_D1 & !_LC6_D1;
-- Node name is '|CNT300:15|:7' = '|CNT300:15|cnt4'
-- Equation name is '_LC8_D9', type is buried
_LC8_D9 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_D1 & !_LC2_D1 & _LC8_D9
# _LC1_D1 & !_LC2_D1 & !_LC8_D9;
-- Node name is '|CNT300:15|:6' = '|CNT300:15|cnt5'
-- Equation name is '_LC3_D9', type is buried
_LC3_D9 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC2_D1 & _LC3_D9 & !_LC8_D9
# !_LC1_D1 & !_LC2_D1 & _LC3_D9
# _LC1_D1 & !_LC2_D1 & !_LC3_D9 & _LC8_D9;
-- Node name is '|CNT300:15|:5' = '|CNT300:15|cnt6'
-- Equation name is '_LC4_D9', type is buried
_LC4_D9 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC1_D9 & !_LC2_D1 & _LC4_D9
# _LC1_D9 & !_LC2_D1 & !_LC4_D9;
-- Node name is '|CNT300:15|:4' = '|CNT300:15|cnt7'
-- Equation name is '_LC5_D9', type is buried
_LC5_D9 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC2_D1 & !_LC4_D9 & _LC5_D9
# !_LC1_D9 & !_LC2_D1 & _LC5_D9
# _LC1_D9 & !_LC2_D1 & _LC4_D9 & !_LC5_D9;
-- Node name is '|CNT300:15|:3' = '|CNT300:15|cnt8'
-- Equation name is '_LC7_D9', type is buried
_LC7_D9 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC2_D1 & !_LC5_D9 & _LC7_D9
# !_LC2_D1 & !_LC6_D9 & _LC7_D9
# !_LC2_D1 & _LC5_D9 & _LC6_D9 & !_LC7_D9;
-- Node name is '|CNT300:15|LPM_ADD_SUB:104|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_D1', type is buried
_LC5_D1 = LCELL( _EQ009);
_EQ009 = _LC2_D8 & _LC7_D1 & _LC8_D1;
-- Node name is '|CNT300:15|LPM_ADD_SUB:104|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_D1', type is buried
_LC1_D1 = LCELL( _EQ010);
_EQ010 = _LC2_D8 & _LC6_D1 & _LC7_D1 & _LC8_D1;
-- Node name is '|CNT300:15|LPM_ADD_SUB:104|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_D9', type is buried
_LC1_D9 = LCELL( _EQ011);
_EQ011 = _LC1_D1 & _LC3_D9 & _LC8_D9;
-- Node name is '|CNT300:15|LPM_ADD_SUB:104|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_D9', type is buried
_LC6_D9 = LCELL( _EQ012);
_EQ012 = _LC1_D9 & _LC4_D9;
-- Node name is '|CNT300:15|~49~1'
-- Equation name is '_LC2_D9', type is buried
-- synthesized logic cell
_LC2_D9 = LCELL( _EQ013);
_EQ013 = _LC4_D9
# _LC5_D9
# !_LC7_D9;
-- Node name is '|CNT300:15|~49~2'
-- Equation name is '_LC4_D1', type is buried
-- synthesized logic cell
_LC4_D1 = LCELL( _EQ014);
_EQ014 = !_LC3_D9
# _LC2_D9
# !_LC6_D1
# _LC8_D9;
-- Node name is '|CNT300:15|:49'
-- Equation name is '_LC2_D1', type is buried
!_LC2_D1 = _LC2_D1~NOT;
_LC2_D1~NOT = LCELL( _EQ015);
_EQ015 = _LC8_D1
# !_LC2_D8
# !_LC7_D1
# _LC4_D1;
-- Node name is '|delay:16|:38' = '|delay:16|clkout'
-- Equation name is '_LC6_E27', type is buried
_LC6_E27 = DFFE( _LC5_E27, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|delay:16|:1'
-- Equation name is '_LC3_D1', type is buried
_LC3_D1 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = _LC2_D8 & !_LC4_D1 & _LC7_D1 & !_LC8_D1;
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