qout.vhd

dds信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qout is
port(clk4:in bit;
      q:out std_logic_vector(1 downto 0));
end;
architecture one of qout is
signal q1:std_logic_vector(1 downto 0);
begin
process(clk4)
begin
   if clk4'event and clk4='1' then 
     q1<=q1+1;
   end if;
end process;
q<=q1;
end;