📄 adder26b.rpt
字号:
69 - - - 06 INPUT ^ 0 0 0 2 B26B27
120 - - - 09 INPUT ^ 0 0 0 2 B26B28
111 - - - 02 INPUT ^ 0 0 0 1 B26B29
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\sin\adder26b.rpt
adder26b
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
42 - - - 19 OUTPUT 0 1 0 0 S26B0
41 - - - 20 OUTPUT 0 1 0 0 S26B1
14 - - A -- OUTPUT 0 1 0 0 S26B2
13 - - A -- OUTPUT 0 1 0 0 S26B3
39 - - - 21 OUTPUT 0 1 0 0 S26B4
144 - - - 24 OUTPUT 0 1 0 0 S26B5
143 - - - 24 OUTPUT 0 1 0 0 S26B6
9 - - A -- OUTPUT 0 1 0 0 S26B7
37 - - - 23 OUTPUT 0 1 0 0 S26B8
117 - - - 06 OUTPUT 0 1 0 0 S26B9
96 - - A -- OUTPUT 0 1 0 0 S26B10
119 - - - 08 OUTPUT 0 1 0 0 S26B11
95 - - A -- OUTPUT 0 1 0 0 S26B12
100 - - A -- OUTPUT 0 1 0 0 S26B13
63 - - - 11 OUTPUT 0 1 0 0 S26B14
122 - - - 12 OUTPUT 0 1 0 0 S26B15
62 - - - 11 OUTPUT 0 1 0 0 S26B16
30 - - C -- OUTPUT 0 1 0 0 S26B17
29 - - C -- OUTPUT 0 1 0 0 S26B18
27 - - C -- OUTPUT 0 1 0 0 S26B19
26 - - C -- OUTPUT 0 1 0 0 S26B20
32 - - C -- OUTPUT 0 1 0 0 S26B21
19 - - B -- OUTPUT 0 1 0 0 S26B22
17 - - B -- OUTPUT 0 1 0 0 S26B23
18 - - B -- OUTPUT 0 1 0 0 S26B24
92 - - B -- OUTPUT 0 1 0 0 S26B25
91 - - B -- OUTPUT 0 1 0 0 S26B26
90 - - B -- OUTPUT 0 1 0 0 S26B27
88 - - B -- OUTPUT 0 1 0 0 S26B28
68 - - - 07 OUTPUT 0 1 0 0 S26B29
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\sin\adder26b.rpt
adder26b
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 20 OR2 4 0 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry1
- 1 - A 21 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry2
- 2 - A 21 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry3
- 3 - A 21 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry4
- 4 - A 23 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry5
- 6 - A 23 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry6
- 8 - A 23 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry7
- 2 - A 23 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry8
- 2 - A 05 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry9
- 3 - A 08 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry10
- 4 - A 08 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry11
- 1 - A 08 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry12
- 6 - A 12 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry13
- 7 - A 12 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry14
- 8 - A 12 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry15
- 3 - A 12 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry16
- 6 - C 23 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry17
- 7 - C 23 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry18
- 8 - C 23 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry19
- 3 - C 23 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry20
- 1 - C 22 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry21
- 5 - B 21 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry22
- 6 - B 21 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry23
- 4 - B 21 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry24
- 5 - B 06 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry25
- 7 - B 06 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry26
- 8 - B 06 OR2 2 1 0 2 |LPM_ADD_SUB:91|addcore:adder|pcarry27
- 2 - B 06 OR2 2 1 0 1 |LPM_ADD_SUB:91|addcore:adder|pcarry28
- 3 - A 20 OR2 2 0 1 0 |LPM_ADD_SUB:91|addcore:adder|:273
- 2 - A 20 OR2 4 0 1 0 |LPM_ADD_SUB:91|addcore:adder|:304
- 8 - A 21 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:305
- 7 - A 21 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:306
- 4 - A 21 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:307
- 7 - A 23 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:308
- 1 - A 23 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:309
- 3 - A 23 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:310
- 5 - A 23 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:311
- 1 - A 05 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:312
- 7 - A 08 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:313
- 2 - A 08 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:314
- 8 - A 08 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:315
- 2 - A 12 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:316
- 5 - A 12 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:317
- 1 - A 12 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:318
- 4 - A 12 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:319
- 5 - C 23 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:320
- 4 - C 23 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:321
- 2 - C 23 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:322
- 1 - C 23 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:323
- 6 - C 22 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:324
- 3 - B 21 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:325
- 1 - B 21 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:326
- 2 - B 21 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:327
- 4 - B 06 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:328
- 1 - B 06 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:329
- 3 - B 06 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:330
- 6 - B 06 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:331
- 1 - B 08 OR2 2 1 1 0 |LPM_ADD_SUB:91|addcore:adder|:332
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\sin\adder26b.rpt
adder26b
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 11/ 96( 11%) 13/ 48( 27%) 15/ 48( 31%) 6/16( 37%) 6/16( 37%) 0/16( 0%)
B: 6/ 96( 6%) 12/ 48( 25%) 8/ 48( 16%) 4/16( 25%) 7/16( 43%) 0/16( 0%)
C: 8/ 96( 8%) 0/ 48( 0%) 9/ 48( 18%) 6/16( 37%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
08: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
12: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
21: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\sin\adder26b.rpt
adder26b
** EQUATIONS **
A26B0 : INPUT;
A26B1 : INPUT;
A26B2 : INPUT;
A26B3 : INPUT;
A26B4 : INPUT;
A26B5 : INPUT;
A26B6 : INPUT;
A26B7 : INPUT;
A26B8 : INPUT;
A26B9 : INPUT;
A26B10 : INPUT;
A26B11 : INPUT;
A26B12 : INPUT;
A26B13 : INPUT;
A26B14 : INPUT;
A26B15 : INPUT;
A26B16 : INPUT;
A26B17 : INPUT;
A26B18 : INPUT;
A26B19 : INPUT;
A26B20 : INPUT;
A26B21 : INPUT;
A26B22 : INPUT;
A26B23 : INPUT;
A26B24 : INPUT;
A26B25 : INPUT;
A26B26 : INPUT;
A26B27 : INPUT;
A26B28 : INPUT;
A26B29 : INPUT;
B26B0 : INPUT;
B26B1 : INPUT;
B26B2 : INPUT;
B26B3 : INPUT;
B26B4 : INPUT;
B26B5 : INPUT;
B26B6 : INPUT;
B26B7 : INPUT;
B26B8 : INPUT;
B26B9 : INPUT;
B26B10 : INPUT;
B26B11 : INPUT;
B26B12 : INPUT;
B26B13 : INPUT;
B26B14 : INPUT;
B26B15 : INPUT;
B26B16 : INPUT;
B26B17 : INPUT;
B26B18 : INPUT;
B26B19 : INPUT;
B26B20 : INPUT;
B26B21 : INPUT;
B26B22 : INPUT;
B26B23 : INPUT;
B26B24 : INPUT;
B26B25 : INPUT;
B26B26 : INPUT;
B26B27 : INPUT;
B26B28 : INPUT;
B26B29 : INPUT;
-- Node name is 'S26B0'
-- Equation name is 'S26B0', type is output
S26B0 = _LC3_A20;
-- Node name is 'S26B1'
-- Equation name is 'S26B1', type is output
S26B1 = _LC2_A20;
-- Node name is 'S26B2'
-- Equation name is 'S26B2', type is output
S26B2 = _LC8_A21;
-- Node name is 'S26B3'
-- Equation name is 'S26B3', type is output
S26B3 = _LC7_A21;
-- Node name is 'S26B4'
-- Equation name is 'S26B4', type is output
S26B4 = _LC4_A21;
-- Node name is 'S26B5'
-- Equation name is 'S26B5', type is output
S26B5 = _LC7_A23;
-- Node name is 'S26B6'
-- Equation name is 'S26B6', type is output
S26B6 = _LC1_A23;
-- Node name is 'S26B7'
-- Equation name is 'S26B7', type is output
S26B7 = _LC3_A23;
-- Node name is 'S26B8'
-- Equation name is 'S26B8', type is output
S26B8 = _LC5_A23;
-- Node name is 'S26B9'
-- Equation name is 'S26B9', type is output
S26B9 = _LC1_A5;
-- Node name is 'S26B10'
-- Equation name is 'S26B10', type is output
S26B10 = _LC7_A8;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -