📄 adder26b.rpt
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Project Information f:\sin\adder26b.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/02/2006 09:45:09
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
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***** Project compilation was successful
ADDER26B
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
adder26b EP1K10TC144-1 60 30 0 0 0 % 58 10 %
User Pins: 60 30 0
Project Information f:\sin\adder26b.rpt
** PROJECT TIMING MESSAGES **
Warning: Timing characteristics of device EP1K10TC144-1 are preliminary
Project Information f:\sin\adder26b.rpt
** FILE HIERARCHY **
|lpm_add_sub:91|
|lpm_add_sub:91|addcore:adder|
|lpm_add_sub:91|altshift:result_ext_latency_ffs|
|lpm_add_sub:91|altshift:carry_ext_latency_ffs|
|lpm_add_sub:91|altshift:oflow_ext_latency_ffs|
Device-Specific Information: f:\sin\adder26b.rpt
adder26b
***** Logic for device 'adder26b' compiled without errors.
Device: EP1K10TC144-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
Device-Specific Information: f:\sin\adder26b.rpt
adder26b
** ERROR SUMMARY **
Info: Chip 'adder26b' in device 'EP1K10TC144-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
B A B A B V S B S A A A B B B A
S S B A 2 2 2 2 2 V B B A B A C B A A 2 A 2 2 B S 2 V 2 2 2 2 2 2
2 2 2 2 6 6 6 6 6 C 2 2 2 2 2 C 2 2 2 6 2 6 6 2 2 6 C 6 6 6 6 6 6
6 6 6 6 B G B B B B C 6 6 6 6 G 6 I 6 6 6 G B 6 B B 6 6 B C B B B B B B
B B B B 1 N 2 2 2 2 I B B B B N B N B B B N 1 B 2 1 B B 1 I 1 1 1 2 2 2
5 6 6 5 8 D 2 3 4 4 O 7 3 4 4 D 3 T 1 2 1 D 5 9 8 1 9 9 6 O 2 5 0 9 6 9
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | N.C.
N.C. | 6 103 | VCCINT
A26B13 | 7 102 | B26B14
B26B13 | 8 101 | N.C.
S26B7 | 9 100 | S26B13
N.C. | 10 99 | N.C.
B26B11 | 11 98 | B26B15
N.C. | 12 97 | A26B14
S26B3 | 13 96 | S26B10
S26B2 | 14 95 | S26B12
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
S26B23 | 17 92 | S26B25
S26B24 | 18 91 | S26B26
S26B22 | 19 EP1K10TC144-1 90 | S26B27
N.C. | 20 89 | N.C.
A26B25 | 21 88 | S26B28
N.C. | 22 87 | B26B25
B26B22 | 23 86 | A26B23
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
S26B20 | 26 83 | B26B17
S26B19 | 27 82 | N.C.
N.C. | 28 81 | A26B17
S26B18 | 29 80 | B26B19
S26B17 | 30 79 | A26B18
N.C. | 31 78 | A26B21
S26B21 | 32 77 | ^MSEL0
A26B19 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
A26B20 | 36 73 | A26B10
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
S B S G S S A B V A R B B V A G V B B A G G A A V S S A R G B S B B V A
2 2 2 N 2 2 2 2 C 2 E 2 2 C 2 N C 2 2 2 N N 2 2 C 2 2 2 E N 2 2 2 2 C 2
6 6 6 D 6 6 6 6 C 6 S 6 6 C 6 D C 6 6 6 D D 6 6 C 6 6 6 S D 6 6 6 6 C 6
B B B B B B B I B E B B I B _ B B B _ B B I B B B E B B B B I B
8 2 4 1 0 6 2 O 7 R 5 8 N 8 C 0 2 0 C 2 2 O 1 1 2 R 1 2 2 1 O 1
1 0 V T K K 7 6 6 4 8 V 2 9 7 6 1
E L L E
D K K D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\sin\adder26b.rpt
adder26b
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A5 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A8 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
A12 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
A20 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A21 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
A23 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
B6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B21 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
C22 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 84/86 ( 97%)
Total logic cells used: 58/576 ( 10%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.01/4 ( 75%)
Total fan-in: 175/2304 ( 7%)
Total input pins required: 60
Total input I/O cell registers required: 0
Total output pins required: 30
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 58
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 2 0 0 6 0 0 0 8 0 0 0 0 0 0 0 0 3 6 0 8 0 33/0
B: 0 0 0 0 0 8 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 15/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 0 10/0
Total: 0 0 0 0 2 8 0 7 0 0 0 8 0 0 0 0 0 0 0 0 3 12 2 16 0 58/0
Device-Specific Information: f:\sin\adder26b.rpt
adder26b
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
56 - - - -- INPUT ^ 0 0 0 3 A26B0
124 - - - -- INPUT ^ 0 0 0 2 A26B1
125 - - - -- INPUT ^ 0 0 0 2 A26B2
128 - - - 13 INPUT ^ 0 0 0 2 A26B3
131 - - - 15 INPUT ^ 0 0 0 2 A26B4
141 - - - 22 INPUT ^ 0 0 0 2 A26B5
43 - - - 18 INPUT ^ 0 0 0 2 A26B6
46 - - - 17 INPUT ^ 0 0 0 2 A26B7
51 - - - 13 INPUT ^ 0 0 0 2 A26B8
121 - - - 10 INPUT ^ 0 0 0 2 A26B9
73 - - - 02 INPUT ^ 0 0 0 2 A26B10
72 - - - 04 INPUT ^ 0 0 0 2 A26B11
114 - - - 04 INPUT ^ 0 0 0 2 A26B12
7 - - A -- INPUT ^ 0 0 0 2 A26B13
97 - - A -- INPUT ^ 0 0 0 2 A26B14
113 - - - 03 INPUT ^ 0 0 0 2 A26B15
116 - - - 05 INPUT ^ 0 0 0 2 A26B16
81 - - C -- INPUT ^ 0 0 0 2 A26B17
79 - - C -- INPUT ^ 0 0 0 2 A26B18
33 - - C -- INPUT ^ 0 0 0 2 A26B19
36 - - - 24 INPUT ^ 0 0 0 2 A26B20
78 - - C -- INPUT ^ 0 0 0 2 A26B21
138 - - - 20 INPUT ^ 0 0 0 2 A26B22
86 - - B -- INPUT ^ 0 0 0 2 A26B23
136 - - - 19 INPUT ^ 0 0 0 2 A26B24
21 - - B -- INPUT ^ 0 0 0 2 A26B25
60 - - - 12 INPUT ^ 0 0 0 2 A26B26
59 - - - 12 INPUT ^ 0 0 0 2 A26B27
64 - - - 10 INPUT ^ 0 0 0 2 A26B28
109 - - - 01 INPUT ^ 0 0 0 1 A26B29
54 - - - -- INPUT ^ 0 0 0 3 B26B0
126 - - - -- INPUT ^ 0 0 0 2 B26B1
55 - - - -- INPUT ^ 0 0 0 2 B26B2
132 - - - 16 INPUT ^ 0 0 0 2 B26B3
130 - - - 14 INPUT ^ 0 0 0 2 B26B4
48 - - - 15 INPUT ^ 0 0 0 2 B26B5
142 - - - 23 INPUT ^ 0 0 0 2 B26B6
133 - - - 17 INPUT ^ 0 0 0 2 B26B7
49 - - - 14 INPUT ^ 0 0 0 2 B26B8
118 - - - 07 INPUT ^ 0 0 0 2 B26B9
112 - - - 03 INPUT ^ 0 0 0 2 B26B10
11 - - A -- INPUT ^ 0 0 0 2 B26B11
67 - - - 08 INPUT ^ 0 0 0 2 B26B12
8 - - A -- INPUT ^ 0 0 0 2 B26B13
102 - - A -- INPUT ^ 0 0 0 2 B26B14
98 - - A -- INPUT ^ 0 0 0 2 B26B15
70 - - - 05 INPUT ^ 0 0 0 2 B26B16
83 - - C -- INPUT ^ 0 0 0 2 B26B17
140 - - - 21 INPUT ^ 0 0 0 2 B26B18
80 - - C -- INPUT ^ 0 0 0 2 B26B19
44 - - - 18 INPUT ^ 0 0 0 2 B26B20
38 - - - 22 INPUT ^ 0 0 0 2 B26B21
23 - - B -- INPUT ^ 0 0 0 2 B26B22
137 - - - 19 INPUT ^ 0 0 0 2 B26B23
135 - - - 18 INPUT ^ 0 0 0 2 B26B24
87 - - B -- INPUT ^ 0 0 0 2 B26B25
110 - - - 01 INPUT ^ 0 0 0 2 B26B26
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