fshow.vhd

dds信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fshow is
port(clk3,clk2,clk1,clk0:in std_logic;
     f: out std_logic_vector(15 downto 0);
     m4:out std_logic_vector(9 downto 0));
end;
architecture one of fshow is
signal f3,f2,f1,f0:std_logic_vector(3 downto 0);
signal m3,m2,m1,m0:std_logic_vector(9 downto 0);
signal m5:std_logic_vector(9 downto 0);
signal f4:std_logic_vector(15 downto 0);
begin
process(clk3)
begin
if clk3'event and clk3='1' then
     if f3="0001" then f3<="0000";m3<=m3-1000;
     else f3<=f3+1;m3<=m3+1000;
     end if;
end if;
end process;
process(clk2)
begin
if clk2'event and clk2='1' then
     if f2="1001" then f2<="0000";m2<=m2-900;
     else f2<=f2+1;m2<=m2+100;
     end if;
end if;
end process;
process(clk1)
begin
if clk1'event and clk1='1' then
     if f1="1001" then f1<="0000";m1<=m1-90;
     else f1<=f1+1;m1<=m1+10;
     end if;
end if;
end process;
process(clk0)
begin
if clk0'event and clk0='1' then
     if f0="1001" then f0<="0000";m0<=m0-9;
     else f0<=f0+1;m0<=m0+1;
     end if;
end if;
end process;
f4<=f3&f2&f1&f0;
m5<=m3+m2+m1+m0;
process(f4)
begin 
if f4<"0000000000010000" then f<="0000000000010000"; m4<="0000001010";
    elsif f4>"0001000000000000" then f<="0001000000000000";m4<="1111101000";
   else f<=f4;m4<=m5;
   end if;
end process;
end;