sub8b.vhd

来自「dds信号发生器」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sub8b is
port(suba:in std_logic_vector(7 downto 0);
      subb:in std_logic_vector(6 downto 0);
     subn:out std_logic_vector(7 downto 0));
end;
architecture one of sub8b is
begin
subn<=suba-subb;
end;