test.vhd

来自「dds信号发生器」· VHDL 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;
entity test is
port(dout:out std_logic_vector(7 downto 0));
end;
architecture one of test is
begin 
    dout<="11111111";
end;